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.Manual Cache Clear/Reload
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.Manual Cache Clear/Reload
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[NOTE]
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[NOTE]
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By executing the `ifence.i` instruction (`Zifencei` CPU extension) the cache is cleared and a reload from
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By executing the `ifence.i` instruction (`Zifencei` CPU extension) the cache is cleared and a reload from
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main memory is triggered. Among other things this allows to implement self-modifying code.
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main memory is triggered. Among other things this allows to implement self-modifying code.
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.Retrieve Cache Configuration from Software
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[TIP]
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Software can retrieve the cache configuration from the <<_sysinfo_cache_configuration>> register.
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**Bus Access Fault Handling**
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**Bus Access Fault Handling**
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The cache always loads a complete cache block (_ICACHE_BLOCK_SIZE_ bytes) aligned to it's size every time a
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The cache always loads a complete cache block (_ICACHE_BLOCK_SIZE_ bytes) aligned to it's size every time a
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cache miss is detected. If any of the accessed addresses within a single block do not successfully
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cache miss is detected. If any of the accessed addresses within a single block do not successfully
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acknowledge the transfer (i.e. issuing an error signal or timing out) the whole cache block is invalidated and
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acknowledge the transfer (i.e. issuing an error signal or timing out) the whole cache block is invalidated and
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