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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_neoled.adoc] - Diff between revs 69 and 73
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Rev 73 |
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If _NEOLED_CTRL_IRQ_CONF_ is cleared, an interrupt is generated whenever the TX FIFO _becomes_ less than half-full.
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If _NEOLED_CTRL_IRQ_CONF_ is cleared, an interrupt is generated whenever the TX FIFO _becomes_ less than half-full.
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In this case software can write up to _IO_NEOLED_TX_FIFO_/2 new data words to `DATA` without checking the FIFO
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In this case software can write up to _IO_NEOLED_TX_FIFO_/2 new data words to `DATA` without checking the FIFO
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status flags. If _NEOLED_CTRL_IRQ_CONF_ is set, an interrupt is generated whenever the TX FIFO _becomes_ empty.
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status flags. If _NEOLED_CTRL_IRQ_CONF_ is set, an interrupt is generated whenever the TX FIFO _becomes_ empty.
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One the NEOLED interrupt has been triggered and became pending, it has to explicitly cleared again by setting the
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One the NEOLED interrupt has been triggered and became pending, it has to explicitly cleared again by
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according `mip` CSR bit.
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writing zero to according <<_mip>> CSR bit.
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[NOTE]
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[NOTE]
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The _NEOLED_CTRL_IRQ_CONF_ is hardwired to one if _IO_NEOLED_TX_FIFO_ = 1 (-> IRQ if FIFO is empty).
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The _NEOLED_CTRL_IRQ_CONF_ is hardwired to one if _IO_NEOLED_TX_FIFO_ = 1 (-> IRQ if FIFO is empty).
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If the FIFO is configured to contain only a single entry (_IO_NEOLED_TX_FIFO_ = 1) the interrupt
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If the FIFO is configured to contain only a single entry (_IO_NEOLED_TX_FIFO_ = 1) the interrupt
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will become pending if the FIFO (which is just a single register providing simple _double-buffering_) is empty.
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will become pending if the FIFO (which is just a single register providing simple _double-buffering_) is empty.
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