| Line 22... |
Line 22... |
bit true color, to dim LCD back-lights or even for "analog" control. An external integrator (RC low-pass filter)
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bit true color, to dim LCD back-lights or even for "analog" control. An external integrator (RC low-pass filter)
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can be used to smooth the generated "analog" signals.
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can be used to smooth the generated "analog" signals.
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**Theory of Operation**
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**Theory of Operation**
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The PWM controller is activated by setting the _PWM_CT_EN_ bit in the module's control register _PWM_CT_. When this
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The PWM controller is activated by setting the _PWM_CTRL_EN_ bit in the module's control register `CTRL`. When this
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bit is cleared, the unit is reset and all PWM output channels are set to zero.
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bit is cleared, the unit is reset and all PWM output channels are set to zero.
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The 8-bit duty cycle for each channel, which represents the channel's "intensity", is defined via an 8-bit value. The module
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The 8-bit duty cycle for each channel, which represents the channel's "intensity", is defined via an 8-bit value. The module
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provides up to 15 duty cycle registers _PWM_DUTY0_ to _PWM_DUTY14_ (depending on the number of implemented channels).
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provides up to 15 duty cycle registers `DUTY[0]` to `DUTY[14]` (depending on the number of implemented channels).
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Each register contains the duty cycle configuration for 4 consecutive channels. For example, the duty cycle of channel 0
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Each register contains the duty cycle configuration for 4 consecutive channels. For example, the duty cycle of channel 0
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is defined via bits 7:0 in _PWM_DUTY0_. The duty cycle of channel 2 is defined via bits 15:0 in _PWM_DUTY0_.
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is defined via bits 7:0 in `DUTY[0]`. The duty cycle of channel 2 is defined via bits 15:0 in `DUTY[0]`.
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Channel 4's duty cycle is defined via bits 7:0 in _PWM_DUTY1_ and so on.
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Channel 4's duty cycle is defined via bits 7:0 in `DUTY[1]` and so on.
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[NOTE]
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[NOTE]
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Regardless of the configuration of _IO_PWM_NUM_CH_ all module registers can be accessed without raising an exception.
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Regardless of the configuration of _IO_PWM_NUM_CH_ all module registers can be accessed without raising an exception.
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Software can discover the number of available channels by writing 0xff to all duty cycle configuration bytes and
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Software can discover the number of available channels by writing 0xff to all duty cycle configuration bytes and
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reading those values back. The duty-cycle of channels that were not implemented always reads as zero.
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reading those values back. The duty-cycle of channels that were not implemented always reads as zero.
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Based on the configured duty cycle the according intensity of the channel can be computed by the following formula:
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Based on the configured duty cycle the according intensity of the channel can be computed by the following formula:
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_**Intensity~x~**_ = _PWM_DUTY_CHx_ / (2^8^)
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_**Intensity~x~**_ = `DUTY[y](i*8+7 downto i*8)` / (2^8^)
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The base frequency of the generated PWM signals is defined by the PWM core clock. This clock is derived
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The base frequency of the generated PWM signals is defined by the PWM core clock. This clock is derived
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from the main processor clock and divided by a prescaler via the 3-bit PWM_CT_PRSCx in the unit's control
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from the main processor clock and divided by a prescaler via the 3-bit PWM_CTRL_PRSCx in the unit's control
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register. The following prescalers are available:
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register. The following prescalers are available:
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.PWM prescaler configuration
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.PWM prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| **`PWM_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| **`PWM_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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|=======================
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The resulting PWM base frequency is defined by:
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The resulting PWM base frequency is defined by:
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_**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`)
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_**f~PWM~**_ = _f~main~[Hz]_ / (2^8^ * `clock_prescaler`)
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.PWM register map
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.PWM register map (`struct neorv32_pwm_t`)
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[cols="<4,<4,<6,^2,<8"]
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[cols="<4,<4,<6,^2,<8"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.4+<| `0xfffffe80` .4+<| _PWM_CT_ <|`0` _PWM_CT_EN_ ^| r/w | PWM enable
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.4+<| `0xfffffe80` .4+<| `NEORV32_PWM.CTRL` <|`0` _PWM_CTRL_EN_ ^| r/w | PWM enable
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<|`1` _PWM_CT_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`1` _PWM_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`2` _PWM_CT_PRSC1_ ^| r/w
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<|`2` _PWM_CTRL_PRSC1_ ^| r/w
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<|`3` _PWM_CT_PRSC2_ ^| r/w
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<|`3` _PWM_CTRL_PRSC2_ ^| r/w
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.4+<| `0xfffffe84` .4+<| _PWM_DUTY0_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
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.4+<| `0xfffffe84` .4+<| `NEORV32_PWM.DUTY[0]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 0
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<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
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<|`15:8` ^| r/w <| 8-bit duty cycle for channel 1
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<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
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<|`23:16` ^| r/w <| 8-bit duty cycle for channel 2
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<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
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<|`31:24` ^| r/w <| 8-bit duty cycle for channel 3
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| ... | ... | ... | r/w | ...
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| ... | ... | ... | r/w | ...
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.4+<| `0xfffffebc` .4+<| _PWM_DUTY14_ <|`7:0` ^| r/w <| 8-bit duty cycle for channel 56
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.4+<| `0xfffffebc` .4+<| `NEORV32_PWM.DUTY[14]` <|`7:0` ^| r/w <| 8-bit duty cycle for channel 56
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<|`15:8` ^| r/w <| 8-bit duty cycle for channel 57
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<|`15:8` ^| r/w <| 8-bit duty cycle for channel 57
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<|`23:16` ^| r/w <| 8-bit duty cycle for channel 58
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<|`23:16` ^| r/w <| 8-bit duty cycle for channel 58
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<|`31:24` ^| r/w <| 8-bit duty cycle for channel 59
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<|`31:24` ^| r/w <| 8-bit duty cycle for channel 59
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|=======================
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|=======================
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