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Line 20... |
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SPI is a synchronous serial transmission interface. The NEORV32 SPI transceiver allows 8-, 16-, 24- and 32-
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SPI is a synchronous serial transmission interface. The NEORV32 SPI transceiver allows 8-, 16-, 24- and 32-
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bit long transmissions. The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o`
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bit long transmissions. The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o`
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signal.
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signal.
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The SPI unit is enabled via the _SPI_CT_EN_ bit in the _SPI_CT_ control register. The idle clock polarity is configured via the _SPI_CT_CPHA_
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The SPI unit is enabled via the _SPI_CTRL_EN_ bit in the `CTRL` control register. The idle clock polarity is configured via the _SPI_CTRL_CPHA_
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bit and can be low (`0`) or high (`1`) during idle. The data quantity to be transferred within a
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bit and can be low (`0`) or high (`1`) during idle. The data quantity to be transferred within a
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single transmission is defined via the _SPI_CT_SIZEx bits_. The unit supports 8-bit (`00`), 16-bit (`01`), 24-
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single transmission is defined via the _SPI_CTRL_SIZEx bits_. The unit supports 8-bit (`00`), 16-bit (`01`), 24-
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bit (`10`) and 32-bit (`11`) transfers. Whenever a transfer is completed, the "transmission done interrupt" is triggered.
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bit (`10`) and 32-bit (`11`) transfers. Whenever a transfer is completed, the "transmission done interrupt" is triggered.
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A transmission is still in progress as long as the _SPI_CT_BUSY_ flag is set.
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A transmission is still in progress as long as the _SPI_CTRL_BUSY_ flag is set.
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's _SPI_CT_CSx_ bits. When
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's _SPI_CTRL_CSx_ bits. When
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a specifc _SPI_CT_CSx_ bit is **set**, the according chip select line `spi_csn_o(x)` goes **low** (low-active chip select lines).
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a specifc _SPI_CTRL_CSx_ bit is **set**, the according chip select line `spi_csn_o(x)` goes **low** (low-active chip select lines).
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The SPI clock frequency is defined via the 3-bit _SPI_CT_PRSCx_ clock prescaler. The following prescalers
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The SPI clock frequency is defined via the 3-bit _SPI_CTRL_PRSCx_ clock prescaler. The following prescalers
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are available:
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are available:
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.SPI prescaler configuration
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.SPI prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| **`SPI_CT_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| **`SPI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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|=======================
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Based on the _SPI_CT_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's main clock f~main~ and is determined by:
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Based on the _SPI_CTRL_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's main clock f~main~ and is determined by:
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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A transmission is started when writing data to the _SPI_DATA_ register. The data must be LSB-aligned. So if
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A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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into the lowest 8/16/24 bit of _SPI_DATA_. Vice versa, the received data is also always LSB-aligned.
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into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned.
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.SPI register map
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.SPI register map (`struct NEORV32_SPI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.16+<| `0xffffffa8` .16+<| _SPI_CT_ <|`0` _SPI_CT_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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.16+<| `0xffffffa8` .16+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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<|`1` _SPI_CT_CS1_ ^| r/w
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<|`1` _SPI_CTRL_CS1_ ^| r/w
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<|`2` _SPI_CT_CS2_ ^| r/w
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<|`2` _SPI_CTRL_CS2_ ^| r/w
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<|`3` _SPI_CT_CS3_ ^| r/w
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<|`3` _SPI_CTRL_CS3_ ^| r/w
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<|`4` _SPI_CT_CS4_ ^| r/w
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<|`4` _SPI_CTRL_CS4_ ^| r/w
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<|`5` _SPI_CT_CS5_ ^| r/w
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<|`5` _SPI_CTRL_CS5_ ^| r/w
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<|`6` _SPI_CT_CS6_ ^| r/w
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<|`6` _SPI_CTRL_CS6_ ^| r/w
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<|`7` _SPI_CT_CS7_ ^| r/w
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<|`7` _SPI_CTRL_CS7_ ^| r/w
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<|`8` _SPI_CT_EN_ ^| r/w <| SPI enable
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<|`8` _SPI_CTRL_EN_ ^| r/w <| SPI enable
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<|`9` _SPI_CT_CPHA_ ^| r/w <| polarity of `spi_sck_o` when idle
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<|`9` _SPI_CTRL_CPHA_ ^| r/w <| polarity of `spi_sck_o` when idle
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<|`10` _SPI_CT_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`10` _SPI_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`11` _SPI_CT_PRSC1_ ^| r/w
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<|`11` _SPI_CTRL_PRSC1_ ^| r/w
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<|`12` _SPI_CT_PRSC2_ ^| r/w
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<|`12` _SPI_CTRL_PRSC2_ ^| r/w
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<|`14` _SPI_CT_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`14` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`15` _SPI_CT_SIZE1_ ^| r/w
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<|`15` _SPI_CTRL_SIZE1_ ^| r/w
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<|`31` _SPI_CT_BUSY_ ^| r/- <| transmission in progress when set
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<|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set
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| `0xffffffac` | _SPI_DATA_ |`31:0` | r/w | receive/transmit data, LSB-aligned
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| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned
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|=======================
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|=======================
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