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|=======================
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|=======================
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| Hardware source file(s): | neorv32_spi.vhd |
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| Hardware source file(s): | neorv32_spi.vhd |
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| Software driver file(s): | neorv32_spi.c |
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| Software driver file(s): | neorv32_spi.c |
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| | neorv32_spi.h |
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| | neorv32_spi.h |
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| Top entity port: | `spi_sck_o` | 1-bit serial clock output
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| Top entity port: | `spi_sck_o` | 1-bit serial clock output
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| | `spi_sdo_i` | 1-bit serial data output
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| | `spi_sdo_o` | 1-bit serial data output
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| | `spi_sdi_o` | 1-bit serial data input
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| | `spi_sdi_i` | 1-bit serial data input
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| | `spi_csn_i` | 8-bit dedicated chip select (low-active)
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| | `spi_csn_i` | 8-bit dedicated chip select (low-active)
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| Configuration generics: | _IO_SPI_EN_ | implement SPI controller when _true_
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| Configuration generics: | _IO_SPI_EN_ | implement SPI controller when _true_
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| CPU interrupts: | fast IRQ channel 6 | transmission done interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 6 | transmission done interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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SPI is a synchronous serial transmission interface. The NEORV32 SPI transceiver allows 8-, 16-, 24- and 32-
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SPI is a synchronous serial transmission interface for fast on-board communications.
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bit long transmissions. The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o`
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The NEORV32 SPI transceiver supports 8-, 16-, 24- and 32-bit wide transmissions.
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signal.
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The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o` signal, which are
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directly controlled by the SPI module (no additional GPIO required).
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The SPI unit is enabled via the _SPI_CTRL_EN_ bit in the `CTRL` control register. The idle clock polarity is configured via the _SPI_CTRL_CPHA_
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bit and can be low (`0`) or high (`1`) during idle. The data quantity to be transferred within a
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The SPI unit is enabled by setting the _SPI_CTRL_EN_ bit in the `CTRL` control register. No transfer can be initiated
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single transmission is defined via the _SPI_CTRL_SIZEx bits_. The unit supports 8-bit (`00`), 16-bit (`01`), 24-
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and no interrupt request will be triggered if this bit is cleared. Furthermore, a transfer being in process
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bit (`10`) and 32-bit (`11`) transfers. Whenever a transfer is completed, the "transmission done interrupt" is triggered.
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can be terminated at any time by clearing this bit.
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A transmission is still in progress as long as the _SPI_CTRL_BUSY_ flag is set.
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The data quantity to be transferred within a single transmission is defined via the _SPI_CTRL_SIZEx_ bits.
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The SPI module supports 8-bit (`00`), 16-bit (`01`), 24-
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bit (`10`) and 32-bit (`11`) transfers.
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A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned. Application
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software should only actually process the amount of bits that were configured using _SPI_CTRL_SIZEx_ when
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reading `DATA`.
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's
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_SPI_CTRL_CSx_ bits. When a specific _SPI_CTRL_CSx_ bit is **set**, the according chip-select line `spi_csn_o(x)`
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goes **low** (low-active chip-select lines).
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[IMPORTANT]
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Changes to the `CTRL` control register should be made only when the SPI module is idle as they directly effect
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transmissions being in-progress.
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[TIP]
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The actual transmission length is left to the user: after asserting chip-select an arbitrary amount of
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transmission with arbitrary data quantity (_SPI_CTRL_SIZEx_) can be made before de-asserting chip-select again.
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[NOTE]
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The NEORV32 SPI module only supports _host mode_. Transmission are initiated only by the processor's SPI module
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(and not by an external SPI module).
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[NOTE]
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The NEORV32 SPI module only support MSB-first mode. Data can be reversed before writing `DATA` (for TX) / after
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reading `DATA` (for RX) to provide LSB-first transmissions.
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**SPI Clock Configuration**
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's _SPI_CTRL_CSx_ bits. When
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The SPI module supports all _standard SPI clock modes_ (0, 1, 2, 3), which is via the two control register bits
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a specifc _SPI_CTRL_CSx_ bit is **set**, the according chip select line `spi_csn_o(x)` goes **low** (low-active chip select lines).
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_SPI_CTRL_CPHA_ and _SPI_CTRL_CPOL_. The _SPI_CTRL_CPHA_ bit defines the _clock phase_ and the _SPI_CTRL_CPOL_
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bit defines the _clock polarity_.
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The SPI clock frequency is defined via the 3-bit _SPI_CTRL_PRSCx_ clock prescaler. The following prescalers
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.SPI clock modes; image from https://en.wikipedia.org/wiki/File:SPI_timing_diagram2.svg (license: (Wikimedia) https://en.wikipedia.org/wiki/Creative_Commons[Creative Commons] https://creativecommons.org/licenses/by-sa/3.0/deed.en[Attribution-Share Alike 3.0 Unported])
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are available:
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image::SPI_timing_diagram2.wikimedia.png[]
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.SPI standard clock modes
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[cols="<2,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| | Mode 0 | Mode 1 | Mode 2 | Mode 4
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| _SPI_CTRL_CPOL_ | `0` | `0` | `1` | `1`
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| _SPI_CTRL_CPHA_ | `0` | `1` | `0` | `1`
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|=======================
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The SPI clock frequency (`spi_sck_o`) is programmed by the 3-bit _SPI_CTRL_PRSCx_ clock prescaler.
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The following prescalers are available:
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.SPI prescaler configuration
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.SPI prescaler configuration
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[cols="<4,^1,^1,^1,^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| **`SPI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| **`SPI_CTRL_PRSCx`** | `0b000` | `0b001` | `0b010` | `0b011` | `0b100` | `0b101` | `0b110` | `0b111`
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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| Resulting `clock_prescaler` | 2 | 4 | 8 | 64 | 128 | 1024 | 2048 | 4096
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|=======================
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|=======================
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Based on the _SPI_CTRL_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's main clock f~main~ and is determined by:
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Based on the _SPI_CTRL_PRSCx_ configuration, the actual SPI clock frequency f~SPI~ is derived from the processor's
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main clock f~main~ and is determined by:
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if
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Hence, the maximum SPI clock is f~main~ / 4.
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned.
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**SPI Interrupt**
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The SPI module provides a single interrupt to signal "ready for new transmission" to the CPU. Whenever the SPI
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module is currently idle (and enabled), the interrupt request is active. A pending interrupt request is cleared
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by triggering a new SPI transmission or by disabling the SPI module.
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.SPI register map (`struct NEORV32_SPI`)
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.SPI register map (`struct NEORV32_SPI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.16+<| `0xffffffa8` .16+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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.18+<| `0xffffffa8` .18+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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<|`1` _SPI_CTRL_CS1_ ^| r/w
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<|`1` _SPI_CTRL_CS1_ ^| r/w
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<|`2` _SPI_CTRL_CS2_ ^| r/w
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<|`2` _SPI_CTRL_CS2_ ^| r/w
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<|`3` _SPI_CTRL_CS3_ ^| r/w
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<|`3` _SPI_CTRL_CS3_ ^| r/w
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<|`4` _SPI_CTRL_CS4_ ^| r/w
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<|`4` _SPI_CTRL_CS4_ ^| r/w
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<|`5` _SPI_CTRL_CS5_ ^| r/w
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<|`5` _SPI_CTRL_CS5_ ^| r/w
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<|`6` _SPI_CTRL_CS6_ ^| r/w
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<|`6` _SPI_CTRL_CS6_ ^| r/w
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<|`7` _SPI_CTRL_CS7_ ^| r/w
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<|`7` _SPI_CTRL_CS7_ ^| r/w
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<|`8` _SPI_CTRL_EN_ ^| r/w <| SPI enable
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<|`8` _SPI_CTRL_EN_ ^| r/w <| SPI enable
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<|`9` _SPI_CTRL_CPHA_ ^| r/w <| polarity of `spi_sck_o` when idle
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<|`9` _SPI_CTRL_CPHA_ ^| r/w <| clock phase (`0`=sample RX on rising edge & update TX on falling edge; `1`=sample RX on falling edge & update TX on rising edge)
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<|`10` _SPI_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`10` _SPI_CTRL_PRSC0_ ^| r/w .3+| 3-bit clock prescaler select
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<|`11` _SPI_CTRL_PRSC1_ ^| r/w
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<|`11` _SPI_CTRL_PRSC1_ ^| r/w
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<|`12` _SPI_CTRL_PRSC2_ ^| r/w
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<|`12` _SPI_CTRL_PRSC2_ ^| r/w
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<|`14` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`13` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`15` _SPI_CTRL_SIZE1_ ^| r/w
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<|`14` _SPI_CTRL_SIZE1_ ^| r/w
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<|`15` _SPI_CTRL_CPOL_ ^| r/w <| clock polarity
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<|`16` .. `30` ^| r/- <| _reserved, read as zero
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<|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set
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<|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set
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| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned
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| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned
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|=======================
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|=======================
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