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Hence, the maximum SPI clock is f~main~ / 4.
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Hence, the maximum SPI clock is f~main~ / 4.
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**SPI Interrupt**
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**SPI Interrupt**
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The SPI module provides a single interrupt to signal "ready for new transmission" to the CPU. Whenever the SPI
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The SPI module provides a single interrupt to signal "transmission done" to the CPU. Whenever the SPI
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module is currently idle (and enabled), the interrupt request is active. A pending interrupt request is cleared
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module completes the current transfer operation, the interrupt request is set. A pending interrupt request
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by triggering a new SPI transmission or by disabling the SPI module.
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is cleared by any of the following operations:
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* read or write access to `NEORV32_SPI.DATA` (for example to trigger a new transmission)
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* write access to `NEORV32_SPI.CTRL`
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* disabling the SPI module
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[TIP]
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A dummy read from `NEORV32_SPI.DATA` can be executed to acknowledge the interrupt without affecting data
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or the state of the SPI module.
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.SPI register map (`struct NEORV32_SPI`)
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.SPI register map (`struct NEORV32_SPI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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