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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_sysinfo.adoc] - Diff between revs 65 and 66

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Rev 65	Rev 66
Line 45...	Line 45...
`\|=======================`	`\|=======================`
`\| Bit \| Name [C] \| Function`	`\| Bit \| Name [C] \| Function`
\| `0` \| _SYSINFO_CPU_ZICSR_ \| `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)	\| `0` \| _SYSINFO_CPU_ZICSR_ \| `Zicsr` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zicsr>> generic)
\| `1` \| _SYSINFO_CPU_ZIFENCEI_ \| `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)	\| `1` \| _SYSINFO_CPU_ZIFENCEI_ \| `Zifencei` extension (`I` sub-extension) available when set (via top's <<_cpu_extension_riscv_zifencei>> generic)
\| `2` \| _SYSINFO_CPU_ZMMUL_ \| `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)	\| `2` \| _SYSINFO_CPU_ZMMUL_ \| `Zmmul` extension (`M` sub-extension) available when set (via top's <<_cpu_extension_riscv_zmmul>> generic)
\| `3` \| _SYSINFO_CPU_ZBB_ \| `Zbb` extension (`B` sub-extension) available when set (via top's <<_cpu_extension_riscv_zbb>> generic)
\| `5` \| _SYSINFO_CPU_ZFINX_ \| `Zfinx` extension (`F` sub-/alternative-extension) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)	\| `5` \| _SYSINFO_CPU_ZFINX_ \| `Zfinx` extension (`F` sub-/alternative-extension) available when set (via top's <<_cpu_extension_riscv_zfinx>> generic)
\| `6` \| _SYSINFO_CPU_ZXSCNT_ \| Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)	\| `6` \| _SYSINFO_CPU_ZXSCNT_ \| Custom extension - _Small_ CPU counters: `[m]cycle` & `[m]instret` CSRs have less than 64-bit when set (via top's <<_cpu_cnt_width>> generic)
\| `7` \| _SYSINFO_CPU_ZXNOCNT_ \| Custom extension - _NO_ CPU counters: `[m]cycle` & `[m]instret` CSRs are NOT available at all when set (via top's <<_cpu_cnt_width>> generic)	\| `7` \| _SYSINFO_CPU_ZXNOCNT_ \| Custom extension - _NO_ CPU counters: `[m]cycle` & `[m]instret` CSRs are NOT available at all when set (via top's <<_cpu_cnt_width>> generic)
\| `8` \| _SYSINFO_CPU_PMP_ \| `PMP` (physical memory protection) extension available when set (via top's <<_>> generic)	\| `8` \| _SYSINFO_CPU_PMP_ \| `PMP` (physical memory protection) extension available when set (via top's <<_>> generic)
\| `9` \| _SYSINFO_CPU_HPM_ \| `HPM` (hardware performance monitors) extension available when set (via top's <<_>> generic)	\| `9` \| _SYSINFO_CPU_HPM_ \| `HPM` (hardware performance monitors) extension available when set (via top's <<_>> generic)

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