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Line 19... |
The two wire interface - also called "I²C" - is a quite famous interface for connecting several on-board
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The two wire interface - also called "I²C" - is a quite famous interface for connecting several on-board
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components. Since this interface only needs two signals (the serial data line `twi_sda_io` and the serial
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components. Since this interface only needs two signals (the serial data line `twi_sda_io` and the serial
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clock line `twi_scl_io`) - despite of the number of connected devices - it allows easy interconnections of
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clock line `twi_scl_io`) - despite of the number of connected devices - it allows easy interconnections of
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several peripheral nodes.
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several peripheral nodes.
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The NEORV32 TWI implements a **TWI controller**. It features "clock stretching" (if enabled via the control
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The NEORV32 TWI implements a **TWI controller**. It supports "clock so a slow peripheral can halt
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register), so a slow peripheral can halt the transmission by pulling the SCL line low. Currently, **no multi-controller
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the transmission by pulling the SCL line low. Currently, **no multi-controller
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support** is available. Also, the NEORV32 TWI unit cannot operate in peripheral mode.
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support** is available. Also, the NEORV32 TWI unit cannot operate in peripheral mode.
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The TWI is enabled via the _TWI_CTRL_EN_ bit in the `CTRL` control register. The user program can start / stop a
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The TWI is enabled via the _TWI_CTRL_EN_ bit in the `CTRL` control register. The user program can start / stop a
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transmission by issuing a START or STOP condition. These conditions are generated by setting the
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transmission by issuing a START or STOP condition. These conditions are generated by setting the
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according bits (_TWI_CTRL_START_ or _TWI_CTRL_STOP_) in the control register.
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according bits (_TWI_CTRL_START_ or _TWI_CTRL_STOP_) in the control register.
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| Line 68... |
Line 68... |
Based on the _TWI_CTRL_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by:
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Based on the _TWI_CTRL_PRSCx_ configuration, the actual TWI clock frequency f~SCL~ is derived from the processor main clock f~main~ and is determined by:
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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_**f~SCL~**_ = _f~main~[Hz]_ / (4 * `clock_prescaler`)
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**Interrupt**
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**TWI Interrupt**
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The TWI module provides a single interrupt to signal _idle state_ (= read for new transmission) to the CPU. Whenever TWI SPI module
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The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
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is currently idle (and enabled), the interrupt request is active. A pending interrupt request is cleared
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module completes the current operation (generate stop condition, generate start conditions or transfer byte),
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by triggering a new TWI transmission or by disabling the device.
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the interrupt request is set. A pending interrupt request is cleared is cleared by any of
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the following operations:
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* read or write access to `NEORV32_TWI.DATA` (for example to trigger a new transmission)
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* write access to `NEORV32_TWI.CTRL`
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* disabling the TWI module
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[TIP]
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A dummy read from `NEORV32_TWI.DATA` can be executed to acknowledge the interrupt without affecting data
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or the state of the TWI module.
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.TWI register map (`struct NEORV32_TWI`)
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.TWI register map (`struct NEORV32_TWI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.10+<| `0xffffffb0` .10+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable
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.9+<| `0xffffffb0` .9+<| `NEORV32_TWI.CTRL` <|`0` _TWI_CTRL_EN_ ^| r/w <| TWI enable
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<|`1` _TWI_CTRL_START_ ^| r/w <| generate START condition
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<|`1` _TWI_CTRL_START_ ^| r/w <| generate START condition
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<|`2` _TWI_CTRL_STOP_ ^| r/w <| generate STOP condition
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<|`2` _TWI_CTRL_STOP_ ^| r/w <| generate STOP condition
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<|`3` _TWI_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`3` _TWI_CTRL_PRSC0_ ^| r/w .3+<| 3-bit clock prescaler select
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<|`4` _TWI_CTRL_PRSC1_ ^| r/w
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<|`4` _TWI_CTRL_PRSC1_ ^| r/w
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<|`5` _TWI_CTRL_PRSC2_ ^| r/w
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<|`5` _TWI_CTRL_PRSC2_ ^| r/w
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<|`6` _TWI_CTRL_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK")
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<|`6` _TWI_CTRL_MACK_ ^| r/w <| generate controller ACK for each transmission ("MACK")
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<|`7` _TWI_CTRL_CKSTEN_ ^| r/w <| allow clock-stretching by peripherals when set
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<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set
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<|`30` _TWI_CTRL_ACK_ ^| r/- <| ACK received when set
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<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
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<|`31` _TWI_CTRL_BUSY_ ^| r/- <| transfer/START/STOP in progress when set
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| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data
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| `0xffffffb4` | `NEORV32_TWI.DATA` |`7:0` _TWI_DATA_MSB_ : TWI_DATA_LSB_ | r/w | receive/transmit data
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|=======================
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|=======================
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