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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_twi.adoc] - Diff between revs 68 and 69

Rev 68	Rev 69
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`TWI Interrupt`	`TWI Interrupt`

`The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI`	`The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI`
`module completes the current operation (generate stop condition, generate start conditions or transfer byte),`	`module completes the current operation (generate stop condition, generate start conditions or transfer byte),`
`the interrupt request is set. A pending interrupt request is cleared is cleared by any of`	`the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by setting the according`
`the following operations:`	`mip` CSR bit.
* read or write access to `NEORV32_TWI.DATA` (for example to trigger a new transmission)
* write access to `NEORV32_TWI.CTRL`
`* disabling the TWI module`

`[TIP]`
A dummy read from `NEORV32_TWI.DATA` can be executed to acknowledge the interrupt without affecting data
`or the state of the TWI module.`


.TWI register map (`struct NEORV32_TWI`)	.TWI register map (`struct NEORV32_TWI`)
`[cols="<2,<2,<4,^1,<7"]`	`[cols="<2,<2,<4,^1,<7"]`
`[options="header",grid="all"]`	`[options="header",grid="all"]`