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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_twi.adoc] - Diff between revs 69 and 73

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**TWI Interrupt**
**TWI Interrupt**
 
 
The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
The SPI module provides a single interrupt to signal "operation done" to the CPU. Whenever the TWI
module completes the current operation (generate stop condition, generate start conditions or transfer byte),
module completes the current operation (generate stop condition, generate start conditions or transfer byte),
the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by setting the according
the interrupt is triggered. Once triggered, the interrupt has to be explicitly cleared again by
`mip` CSR bit.
writing zero to the according <<_mip>> CSR bit.
 
 
 
 
.TWI register map (`struct NEORV32_TWI`)
.TWI register map (`struct NEORV32_TWI`)
[cols="<2,<2,<4,^1,<7"]
[cols="<2,<2,<4,^1,<7"]
[options="header",grid="all"]
[options="header",grid="all"]

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