| Line 56... |
Line 56... |
transfer is completed when the _UART_CTRL_TX_BUSY_ control register flag returns to zero. A new received byte
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transfer is completed when the _UART_CTRL_TX_BUSY_ control register flag returns to zero. A new received byte
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is available when the _UART_DATA_AVAIL_ flag of the `DATA` register is set. A "frame error" in a received byte
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is available when the _UART_DATA_AVAIL_ flag of the `DATA` register is set. A "frame error" in a received byte
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(invalid stop bit) is indicated via the _UART_DATA_FERR_ flag in the `DATA` register. The flag is cleared by
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(invalid stop bit) is indicated via the _UART_DATA_FERR_ flag in the `DATA` register. The flag is cleared by
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reading the `DATA` register.
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reading the `DATA` register.
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[TIP]
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A transmission (RX or TX) can be terminated at any time by disabling the UART module
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by clearing the _UART_CTRL_EN_ control register bit.
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**RX and TX FIFOs**
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**RX and TX FIFOs**
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UART0 provides optional FIFO buffers for the transmitter and the receiver. The _UART0_RX_FIFO_ generic defines
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UART0 provides optional FIFO buffers for the transmitter and the receiver. The _UART0_RX_FIFO_ generic defines
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the depth of the RX FIFO (for receiving data) while the _UART0_TX_FIFO_ defines the depth of the TX FIFO
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the depth of the RX FIFO (for receiving data) while the _UART0_TX_FIFO_ defines the depth of the TX FIFO
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| Line 71... |
Line 75... |
_UART_CTRL_?X_HALF_ and _UART_CTRL_*X_FULL_ flags in the `CTRL` register.
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_UART_CTRL_?X_HALF_ and _UART_CTRL_*X_FULL_ flags in the `CTRL` register.
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If the RX FIFO is already full and new data is received by the receiver unit, the _UART_DATA_OVERR_ flag
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If the RX FIFO is already full and new data is received by the receiver unit, the _UART_DATA_OVERR_ flag
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in the `DATA` register is set indicating an "overrun". This flag is cleared by reading the `DATA` register.
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in the `DATA` register is set indicating an "overrun". This flag is cleared by reading the `DATA` register.
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[NOTE]
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In contrast to other FIFO-equipped peripherals, software **cannot** determine the UART's FIFO size configuration
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by reading specific control register bits (simply because there are no bits left in the control register).
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**Hardware Flow Control - RTS/CTS**
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**Hardware Flow Control - RTS/CTS**
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UART0 supports optional hardware flow control using the standard CTS (clear to send) and/or RTS (ready to send
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UART0 supports optional hardware flow control using the standard CTS (clear to send) and/or RTS (ready to send
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