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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_uart.adoc] - Diff between revs 72 and 73

Rev 72	Rev 73
Line 127...	Line 127...
`the RX FIFO _becomes_ at least half-full (-> _UART_CTRL_RX_HALF_ sets).`	`the RX FIFO _becomes_ at least half-full (-> _UART_CTRL_RX_HALF_ sets).`
* If _UART0_TX_FIFO_ is greater than 1: If _UART_CTRL_TX_IRQ_ is `0` the TX interrupt goes pending when at least one entry	* If _UART0_TX_FIFO_ is greater than 1: If _UART_CTRL_TX_IRQ_ is `0` the TX interrupt goes pending when at least one entry
in the TX FIFO _becomes_ free (-> _UART_CTRL_TX_FULL_ clears). If _UART_CTRL_TX_IRQ_ is `1` the TX interrupt goes pending	in the TX FIFO _becomes_ free (-> _UART_CTRL_TX_FULL_ clears). If _UART_CTRL_TX_IRQ_ is `1` the TX interrupt goes pending
`when the RX FIFO _becomes_ less than half-full (-> _UART_CTRL_TX_HALF_ clears).`	`when the RX FIFO _becomes_ less than half-full (-> _UART_CTRL_TX_HALF_ clears).`

`Once the RX or TX interrupt has become pending, it has to be explicitly cleared again by setting the`	`Once the RX or TX interrupt has become pending, it has to be explicitly cleared again by`
according `mip` CSR bit.	`writing zero to the according <<_mip>> CSR bit.`


`Simulation Mode`	`Simulation Mode`

The default UART0 operation will transmit any data written to the `DATA` register via the serial TX line at	The default UART0 operation will transmit any data written to the `DATA` register via the serial TX line at