| Line 11... |
Line 11... |
| Top entity port: | none |
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| Top entity port: | none |
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| Configuration generics: | _IO_WDT_EN_ | implement GPIO port when _true_
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| Configuration generics: | _IO_WDT_EN_ | implement GPIO port when _true_
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| CPU interrupts: | fast IRQ channel 0 | watchdog timer overflow (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 0 | watchdog timer overflow (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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**Theory of Operation**
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The watchdog (WDT) provides a last resort for safety-critical applications. The WDT has an internal 20-bit
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The watchdog (WDT) provides a last resort for safety-critical applications. The WDT has an internal 20-bit
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wide counter that needs to be reset every now and then by the user program. If the counter overflows, either
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wide counter that needs to be reset every now and then by the user program. If the counter overflows, either
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a system reset or an interrupt is generated (depending on the configured operation mode).
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a system reset or an interrupt is generated (depending on the configured operation mode).
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The _WDT_CTRL_HALF_ flag of the control register `CTRL` indicates that at least half of the maximum timeout
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value has been reached.
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Configuration of the watchdog is done by a single control register `CTRL`. The watchdog is enabled by
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The watchdog is enabled by setting the _WDT_CTRL_EN_ bit. The clock used to increment the internal counter
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setting the _WDT_CTRL_EN_ bit. The clock used to increment the internal counter is selected via the 3-bit
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is selected via the 3-bit _WDT_CTRL_CLK_SELx_ prescaler:
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_WDT_CTRL_CLK_SELx_ prescaler:
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[cols="^3,^3,>4"]
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[cols="^3,^3,>4"]
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[options="header",grid="rows"]
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[options="header",grid="rows"]
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|=======================
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|=======================
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| **`WDT_CTRL_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles
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| **`WDT_CTRL_CLK_SELx`** | Main clock prescaler | Timeout period in clock cycles
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| Line 42... |
Line 44... |
WDT_CTRL_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will assert an
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WDT_CTRL_MODE bit defines the action to be taken on an overflow: When cleared, the Watchdog will assert an
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IRQ, when set the WDT will cause a system reset. The configured action can also be triggered manually at
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IRQ, when set the WDT will cause a system reset. The configured action can also be triggered manually at
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any time by setting the _WDT_CTRL_FORCE_ bit. The watchdog is reset by setting the _WDT_CTRL_RESET_ bit.
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any time by setting the _WDT_CTRL_FORCE_ bit. The watchdog is reset by setting the _WDT_CTRL_RESET_ bit.
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A watchdog interrupt can only occur if the watchdog is enabled and interrupt mode is enabled.
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A watchdog interrupt can only occur if the watchdog is enabled and interrupt mode is enabled.
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A pending interrupt is cleared by either disabling the watchdog or by resetting the watchdog.
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A triggered interrupt has to be cleared again by setting the according `mip` CSR bit.
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The cause of the last action of the watchdog can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
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The cause of the last action of the watchdog can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
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zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was
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zero, the processor has been reset via the external reset signal. If this flag is set the last system reset was
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initiated by the watchdog.
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initiated by the watchdog.
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The Watchdog control register can be locked in order to protect the current configuration. The lock is
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The Watchdog control register can be locked in order to protect the current configuration. The lock is
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activated by setting bit _WDT_CTRL_LOCK_. In the locked state any write access to the configuration flags is
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activated by setting bit _WDT_CTRL_LOCK_. In the locked state any write access to the configuration flags is
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ignored (see table below, "accessible if locked"). Read accesses to the control register are not effected. The
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ignored (see table below, "writable if locked"). Read accesses to the control register are not effected. The
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lock can only be removed by a system reset (via external reset signal or via a watchdog reset action).
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lock can only be removed by a system reset (via external reset signal or via a watchdog reset action).
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.Watchdog Operation during Debugging
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[IMPORTANT]
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By default the watchdog pauses operation when the CPU enters debug mode and will resume normal operation after
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the CPU has left debug mode. This will prevent an unintended watchdog timeout (and a hardware reset if configured)
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during a debug session. However, the watchdog can be configured to keep operating even when the CPU is in debug
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mode by setting the control register's _WDT_CTRL_DBEN_ bit. If the CPU's debug mode is not implemented this flag
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is hardwired to zero.
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.WDT register map (`struct NEORV32_WDT`)
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.WDT register map (`struct NEORV32_WDT`)
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[cols="<2,<2,<4,^1,^2,<4"]
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[cols="<2,<2,<4,^1,^1,^2,<4"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Writable if locked | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function
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.9+<| `0xffffffbc` .9+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| no <| watchdog enable
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.11+<| `0xffffffbc` .11+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
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<|`1` _WDT_CTRL_CLK_SEL0_ ^| r/w ^| no .3+<| 3-bit clock prescaler select
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<|`1` _WDT_CTRL_CLK_SEL0_ ^| r/w ^| `0` ^| no .3+<| 3-bit clock prescaler select
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<|`2` _WDT_CTRL_CLK_SEL1_ ^| r/w ^| no
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<|`2` _WDT_CTRL_CLK_SEL1_ ^| r/w ^| `0` ^| no
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<|`3` _WDT_CTRL_CLK_SEL2_ ^| r/w ^| no
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<|`3` _WDT_CTRL_CLK_SEL2_ ^| r/w ^| `0` ^| no
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<|`4` _WDT_CTRL_MODE_ ^| r/w ^| no <| overflow action: `1`=reset, `0`=IRQ
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<|`4` _WDT_CTRL_MODE_ ^| r/w ^| `0` ^| no <| overflow action: `1`=reset, `0`=IRQ
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<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
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<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
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<|`6` _WDT_CTRL_RESET_ ^| -/w ^| yes <| watchdog reset when set, auto-clears
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<|`6` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| watchdog reset when set, auto-clears
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<|`7` _WDT_CTRL_FORCE_ ^| -/w ^| yes <| force configured watchdog action when set, auto-clears
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<|`7` _WDT_CTRL_FORCE_ ^| -/w ^| - ^| yes <| force configured watchdog action when set, auto-clears
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<|`8` _WDT_CTRL_LOCK_ ^| r/w ^| no <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset)
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<|`8` _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock access to configuration when set, clears only on system reset (via external reset signal OR watchdog reset action = reset)
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<|`9` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| allow WDT to continue operation even when in debug mode
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<|`10` _WDT_CTRL_HALF_ ^| r/- ^| `0` ^| - <| set if at least half of the max. timeout counter value has been reached
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|=======================
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|=======================
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