| Line 21... |
Line 21... |
| | `fence_o` | an executed `fence` instruction
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| | `fence_o` | an executed `fence` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| Configuration constants in VHDL package file `neorv32_package.vhd`: | `wb_pipe_mode_c` | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| Configuration constants in VHDL package file `neorv32_package.vhd`: | `wb_pipe_mode_c` | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| | `xbus_big_endian_c` | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | `wb_big_endian_c` | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | `wb_rx_buffer_c` | enable register buffer for RX path (default)
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| CPU interrupts: | none |
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| CPU interrupts: | none |
|
|=======================
|
|=======================
|
|
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The external memory interface uses the Wishbone interface protocol. The external interface port is available
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The external memory interface uses the Wishbone interface protocol. The external interface port is available
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when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories, custom
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when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories, custom
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| Line 47... |
Line 48... |
**pipelined** Wishbone transactions. The transaction protocol is configured via the wb_pipe_mode_c constant
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**pipelined** Wishbone transactions. The transaction protocol is configured via the wb_pipe_mode_c constant
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in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
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in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
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|
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[source,vhdl]
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[source,vhdl]
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----
|
----
|
-- (external) bus interface --
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-- external bus interface --
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constant wb_pipe_mode_c : boolean := false;
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constant wb_pipe_mode_c : boolean := false;
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----
|
----
|
|
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When `wb_pipe_mode_c` is disabled, all bus control signals including _STB_ are active (and stable) until the
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When `wb_pipe_mode_c` is disabled, all bus control signals including _STB_ are active (and stable) until the
|
transfer is acknowledged/terminated. If `wb_pipe_mode_c` is enabled, all bus control except _STB_ are active
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transfer is acknowledged/terminated. If `wb_pipe_mode_c` is enabled, all bus control except _STB_ are active
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| Line 74... |
Line 75... |
Architecture for Portable IP Cores". A copy of this document can be found in the docs folder of this
|
Architecture for Portable IP Cores". A copy of this document can be found in the docs folder of this
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project.
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project.
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|
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**Interface Latency**
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**Interface Latency**
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|
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The Wishbone gateway introduces two additional latency cycles: Processor-outgoing and -incoming signals
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By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
|
are fully registered. Thus, any access from the CPU to a processor-external devices requires +2 clock cycles.
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processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
|
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via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
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|
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If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
|
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for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled.
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The configuration is done via the `wb_rx_buffer_c` constant in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
|
|
|
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[source,vhdl]
|
|
----
|
|
-- external bus interface --
|
|
constant wb_rx_buffer_c : boolean := false; -- false to implement "async" RX (non-default)
|
|
----
|
|
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**Bus Access Timeout**
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**Bus Access Timeout**
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|
|
The Wishbone bus interface provides an option to configure a bus access timeout counter. The _MEM_EXT_TIMEOUT_
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The Wishbone bus interface provides an option to configure a bus access timeout counter. The _MEM_EXT_TIMEOUT_
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top generic is used to specify the _maximum_ time (in clock cycles) a bus access can be pending before it is automatically
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top generic is used to specify the _maximum_ time (in clock cycles) a bus access can be pending before it is automatically
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| Line 123... |
Line 135... |
|
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**Endianness**
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**Endianness**
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|
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The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
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The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
|
to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
|
to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
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Endianness (of the external memory interface) can be configured via the global `xbus_big_endian_c`
|
Endianness (of the external memory interface) can be configured via the global `wb_big_endian_c`
|
constant in the main VHDL package file (`rtl/neorv32_package.vhd`). By default, the external memory
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constant in the main VHDL package file (`rtl/neorv32_package.vhd`). By default, the external memory
|
interface uses little-endian byte-order.
|
interface uses little-endian byte-order.
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|
|
[source,vhdl]
|
[source,vhdl]
|
----
|
----
|
-- (external) bus interface --
|
-- external bus interface --
|
constant xbus_big_endian_c : boolean := true;
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constant wb_big_endian_c : boolean := true;
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----
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----
|
|
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Application software can check the Endianness configuration of the external bus interface via the
|
Application software can check the Endianness configuration of the external bus interface via the
|
_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
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_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
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<<_system_configuration_information_memory_sysinfo>> for more information).
|
<<_system_configuration_information_memory_sysinfo>> for more information).
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|
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**AXI4-Lite Connectivity**
|
**AXI4-Lite Connectivity**
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|
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The AXI4-Lite wrapper (`rtl/top_templates/neorv32_top_axi4lite.vhd`) provides a Wishbone-to-
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The AXI4-Lite wrapper (`rtl/templates/system/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
|
AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
|
this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
|
this wrapper are of type _std_logic_ or _std_logic_vector_, respectively.
|
|
|
The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
|
The AXI Interface has been verified using Xilinx Vivado IP Packager and Block Designer. The AXI
|
interface port signals are automatically detected when packaging the core.
|
interface port signals are automatically detected when packaging the core.
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| Line 151... |
Line 163... |
.Example AXI SoC using Xilinx Vivado
|
.Example AXI SoC using Xilinx Vivado
|
image::neorv32_axi_soc.png[]
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image::neorv32_axi_soc.png[]
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[WARNING]
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[WARNING]
|
Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
|
Using the auto-termination timeout feature (_MEM_EXT_TIMEOUT_ greater than zero) is **not AXI4 compliant** as the AXI protocol does not support canceling of
|
bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/top_templates/neorv32_top_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/templates/system/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
|
|
|
|
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bus transactions. Therefore, the NEORV32 top wrapper with AXI4-Lite interface (`rtl/templates/system/neorv32_SystemTop_axi4lite`) configures _MEM_EXT_TIMEOUT_ = 0 by default.
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|
