| Line 20... |
Line 20... |
| | `wb_err_i` | bus error (1-bit)
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| | `wb_err_i` | bus error (1-bit)
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| | `fence_o` | an executed `fence` instruction
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| | `fence_o` | an executed `fence` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| | `fencei_o` | an executed `fence.i` instruction
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| Configuration generics: | _MEM_EXT_EN_ | enable external memory interface when _true_
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
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| | _MEM_EXT_TIMEOUT_ | number of clock cycles after which an unacknowledged external bus access will auto-terminate (0 = disabled)
|
| Configuration constants in VHDL package file `neorv32_package.vhd`: | `wb_pipe_mode_c` | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| | _MEM_EXT_PIPE_MODE_ | when _false_ (default): classic/standard Wishbone protocol; when _true_: pipelined Wishbone protocol
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| | `wb_big_endian_c` | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | _MEM_EXT_BIG_ENDIAN_ | byte-order (Endianness) of external memory interface; true=BIG, false=little (default)
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| | `wb_rx_buffer_c` | enable register buffer for RX path (default)
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| | _MEM_EXT_ASYNC_RX_ | use registered RX path when _false_ (default); use async/direct RX path when _true_
|
| CPU interrupts: | none |
|
| CPU interrupts: | none |
|
|=======================
|
|=======================
|
|
|
The external memory interface uses the Wishbone interface protocol. The external interface port is available
|
The external memory interface uses the Wishbone interface protocol. The external interface port is available
|
when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories, custom
|
when the _MEM_EXT_EN_ generic is _true_. This interface can be used to attach external memories, custom
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| Line 43... |
Line 43... |
(DMEM). See section <<_address_space>> for more information.
|
(DMEM). See section <<_address_space>> for more information.
|
|
|
**Wishbone Bus Protocol**
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**Wishbone Bus Protocol**
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|
|
The external memory interface either uses **standard** ("classic") Wishbone transactions (default) or
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The external memory interface either uses **standard** ("classic") Wishbone transactions (default) or
|
**pipelined** Wishbone transactions. The transaction protocol is configured via the wb_pipe_mode_c constant
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**pipelined** Wishbone transactions. The transaction protocol is configured via the _MEM_EXT_PIPE_MODE_ generic:
|
in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
|
|
|
|
[source,vhdl]
|
When _MEM_EXT_PIPE_MODE_ is _false_, all bus control signals including _STB_ are active (and stable) until the
|
----
|
transfer is acknowledged/terminated. If _MEM_EXT_PIPE_MODE_ is _true_, all bus control except _STB_ are active
|
-- external bus interface --
|
|
constant wb_pipe_mode_c : boolean := false;
|
|
----
|
|
|
|
When `wb_pipe_mode_c` is disabled, all bus control signals including _STB_ are active (and stable) until the
|
|
transfer is acknowledged/terminated. If `wb_pipe_mode_c` is enabled, all bus control except _STB_ are active
|
|
(and stable) until the transfer is acknowledged/terminated. In this case, _STB_ is active only during the very
|
(and stable) until the transfer is acknowledged/terminated. In this case, _STB_ is active only during the very
|
first bus clock cycle.
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first bus clock cycle.
|
|
|
.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
|
.Exemplary Wishbone bus accesses using "classic" and "pipelined" protocol
|
[cols="^2,^2"]
|
[cols="^2,^2"]
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| Line 80... |
Line 73... |
By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
|
By default, the Wishbone gateway introduces two additional latency cycles: processor-outgoing ("TX") and
|
processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
|
processor-incoming ("RX") signals are fully registered. Thus, any access from the CPU to a processor-external devices
|
via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
|
via Wishbone requires 2 additional clock cycles (at least; depending on device's latency).
|
|
|
If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
|
If the attached Wishbone network / peripheral already provides output registers or if the Wishbone network is not relevant
|
for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled.
|
for timing closure, the default buffering of incoming ("RX") data within the gateway can be disabled by implementing an
|
The configuration is done via the `wb_rx_buffer_c` constant in the in the main VHDL package file (`rtl/neorv32_package.vhd`):
|
"asynchronous" RX path. The configuration is done via the _MEM_EXT_ASYNC_RX_ generic.
|
|
|
[source,vhdl]
|
|
----
|
|
-- external bus interface --
|
|
constant wb_rx_buffer_c : boolean := false; -- false to implement "async" RX (non-default)
|
|
----
|
|
|
|
**Bus Access Timeout**
|
**Bus Access Timeout**
|
|
|
The Wishbone bus interface provides an option to configure a bus access timeout counter. The _MEM_EXT_TIMEOUT_
|
The Wishbone bus interface provides an option to configure a bus access timeout counter. The _MEM_EXT_TIMEOUT_
|
top generic is used to specify the _maximum_ time (in clock cycles) a bus access can be pending before it is automatically
|
top generic is used to specify the _maximum_ time (in clock cycles) a bus access can be pending before it is automatically
|
| Line 135... |
Line 122... |
|
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**Endianness**
|
**Endianness**
|
|
|
The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
|
The NEORV32 CPU and the Processor setup are *little-endian* architectures. To allow direct connection
|
to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
|
to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
|
Endianness (of the external memory interface) can be configured via the global `wb_big_endian_c`
|
Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
|
constant in the main VHDL package file (`rtl/neorv32_package.vhd`). By default, the external memory
|
By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
|
interface uses little-endian byte-order.
|
|
|
|
[source,vhdl]
|
|
----
|
|
-- external bus interface --
|
|
constant wb_big_endian_c : boolean := true;
|
|
----
|
|
|
|
Application software can check the Endianness configuration of the external bus interface via the
|
Application software can check the Endianness configuration of the external bus interface via the
|
_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
|
_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
|
<<_system_configuration_information_memory_sysinfo>> for more information).
|
<<_system_configuration_information_memory_sysinfo>> for more information).
|
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|
