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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_wishbone.adoc] - Diff between revs 63 and 64
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to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
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to a big-endian memory system the external bus interface provides an _Endianness configuration_. The
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Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
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Endianness (of the external memory interface) can be configured via the _MEM_EXT_BIG_ENDIAN_ generic.
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By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
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By default, the external memory interface uses little-endian byte-order (like the rest of the processor / CPU).
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Application software can check the Endianness configuration of the external bus interface via the
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Application software can check the Endianness configuration of the external bus interface via the
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_SYSINFO_FEATURES_MEM_EXT_ENDIAN_ flag in the processor's SYSINFO module (see section
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SYSINFO module (see section <<_system_configuration_information_memory_sysinfo>> for more information).
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<<_system_configuration_information_memory_sysinfo>> for more information).
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**AXI4-Lite Connectivity**
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**AXI4-Lite Connectivity**
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The AXI4-Lite wrapper (`rtl/system_integration/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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The AXI4-Lite wrapper (`rtl/system_integration/neorv32_SystemTop_axi4lite.vhd`) provides a Wishbone-to-
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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AXI4-Lite bridge, compatible with Xilinx Vivado (IP packager and block design editor). All entity signals of
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