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[frame="topbot",grid="none"]
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[frame="topbot",grid="none"]
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|=======================
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|=======================
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| Hardware source file(s): | neorv32_xirq.vhd |
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| Hardware source file(s): | neorv32_xirq.vhd |
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| Software driver file(s): | neorv32_xirq.c |
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| Software driver file(s): | neorv32_xirq.c |
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| | neorv32_xirq.h |
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| | neorv32_xirq.h |
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| Top entity port: | `xirq_i` | IRQ input (up to 32-bit)
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| Top entity port: | `xirq_i` | IRQ input (32-bit, fixed)
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| Configuration generics: | _XIRQ_NUM_CH_ | Number of IRQs to implement (0..32)
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| Configuration generics: | _XIRQ_NUM_CH_ | Number of IRQs to implement (0..32)
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| | _XIRQ_TRIGGER_TYPE_ | IRQ trigger type configuration
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| | _XIRQ_TRIGGER_TYPE_ | IRQ trigger type configuration
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| | _XIRQ_TRIGGER_POLARITY_ | IRQ trigger polarity configuration
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| | _XIRQ_TRIGGER_POLARITY_ | IRQ trigger polarity configuration
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| CPU interrupts: | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
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| CPU interrupts: | fast IRQ channel 8 | XIRQ (see <<_processor_interrupts>>)
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|=======================
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|=======================
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single _CPU fast interrupt request_.
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single _CPU fast interrupt request_.
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**Theory of Operation**
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**Theory of Operation**
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The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in the `xirq_i`
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The XIRQ provides up to 32 interrupt _channels_ (configured via the _XIRQ_NUM_CH_ generic). Each bit in the `xirq_i`
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input signal vector represents one interrupt channel. An interrupt channel is enabled by setting the according bit in the
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input signal vector represents one interrupt channel. If less than 32 channels are configure, only the LSB-aligned channels
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are used while the remaining bits are left unconnected. An interrupt channel is enabled by setting the according bit in the
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interrupt enable register `IER`.
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interrupt enable register `IER`.
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If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer.
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If the configured trigger (see below) of an enabled channel fires, the request is stored into an internal buffer.
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This buffer is available via the interrupt pending register `IPR`. A `1` in this register indicates that the
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This buffer is available via the interrupt pending register `IPR`. A `1` in this register indicates that the
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corresponding interrupt channel has fired but has not yet been serviced (so it is pending). An interrupt channel can
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corresponding interrupt channel has fired but has not yet been serviced (so it is pending). An interrupt channel can
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