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[/] [neorv32/] [trunk/] [docs/] [datasheet/] [soc_xirq.adoc] - Diff between revs 70 and 73

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Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
Interrupt channel `xirq_i(0)` has highest priority and `xirq_i(_XIRQ_NUM_CH_-1)` has lowest priority.
This priority assignment is fixed and cannot be altered by software.
This priority assignment is fixed and cannot be altered by software.
The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
The CPU can use the ID from `SCR` to service IRQ according to their priority. To acknowledge the according
interrupt the CPU can write `1 << SCR` to `IPR`.
interrupt the CPU can write `1 << SCR` to `IPR`.
 
 
In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according `mip` CSR bit has
In order to clear a pending FIRQ interrupt from the external interrupt controller again, the according <<_mip>> CSR bit has
to be set. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
to be cleared. Additionally, the XIRQ interrupt has to be acknowledged by writing _any_
value to the interrupt source register `SRC`.
value to the interrupt source register `SRC`.
 
 
[NOTE]
[NOTE]
An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
An interrupt handler should clear the interrupt pending bit that caused the interrupt first before
acknowledging the interrupt by writing the `SCR` register.
acknowledging the interrupt by writing the `SCR` register.

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