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[source,bash]
[source,bash]
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neorv32/sw/example/blink_led$ make check
neorv32/sw/example/blink_led$ make check
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This will test all the tools required for the generating NEORV32 executables.
This will test all the tools required for generating NEORV32 executables.
Everything is working fine if `Toolchain check OK` appears at the end.
Everything is working fine if `Toolchain check OK` appears at the end.
 
 
 
 
 
 
 
 
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:sectnums:
:sectnums:
== General Software Framework Setup
== General Software Framework Setup
 
 
To allow executables to be _actually executed_ on the NEORV32 Processor the configuration of the software framework
To allow executables to be _actually executed_ on the NEORV32 Processor the configuration of the software framework
has to be aware to the hardware configuration. This guide focuses on the memory configuration. To enabled
has to be aware to the hardware configuration. This guide focuses on the memory configuration. To enabled
certain CPU ISA festures refer to the <<_enabling_risc_v_cpu_extensions>> section.
certain CPU ISA features refer to the <<_enabling_risc_v_cpu_extensions>> section.
 
 
[TIP]
[TIP]
If you have **not** changed the _default_ memory configuration in section <<_general_hardware_setup>>
If you have **not** changed the _default_ memory configuration in section <<_general_hardware_setup>>
you are already done and you can skip the rest of this guide.
you are already done and you can skip the rest of this guide.
 
 
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neorv32/sw/example/blink_led$ make clean_all exe
neorv32/sw/example/blink_led$ make clean_all exe
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[start=3]
[start=3]
. We are using the `clean_all` taret to make sure everything is re-build.
. We are using the `clean_all` target to make sure everything is re-build.
. This will compile and link the application sources together with all the included libraries. At the end,
. This will compile and link the application sources together with all the included libraries. At the end,
your application is transformed into an ELF file (`main.elf`). The _NEORV32 image generator_ (in `sw/image_gen`)
your application is transformed into an ELF file (`main.elf`). The _NEORV32 image generator_ (in `sw/image_gen`)
takes this file and creates a final executable. The makefile will show the resulting memory utilization and
takes this file and creates a final executable. The makefile will show the resulting memory utilization and
the executable size:
the executable size:
 
 
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[start=1]
[start=1]
. The easiest way of creating a _new_ software application project is to copy an _existing_ one. This will keep all
. The easiest way of creating a _new_ software application project is to copy an _existing_ one. This will keep all
file dependencies. For example you can copy `sw/example/blink_led` to `sw/example/flux_capacitor`.
file dependencies. For example you can copy `sw/example/blink_led` to `sw/example/flux_capacitor`.
. If you want to place you application somewhere outside `sw/example` you need to adapt the application's makefile.
. If you want to place you application somewhere outside `sw/example` you need to adapt the application's makefile.
In the makefile you will find a variable that keeps the relative or absolute path to the NEORV32 repo home
In the makefile you will find a variable that keeps the relative or absolute path to the NEORV32 repository home
folder. Just modify this variable according to your new project's home location:
folder. Just modify this variable according to your new project's home location:
 
 
[source,makefile]
[source,makefile]
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# Relative or absolute path to the NEORV32 home folder (use default if not set by user)
# Relative or absolute path to the NEORV32 home folder (use default if not set by user)
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allow more CPU-independent operation.
allow more CPU-independent operation.
 
 
 
 
=== Custom Functions Subsystem
=== Custom Functions Subsystem
 
 
The https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[NEORV32 Custom Functions Subsystem]
The NEORV32 https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs[Custom Functions Subsystem] is
is as "empty" template for a processor-internal module. It provides 32 32-bit memory-mapped interface
an "empty" template for a processor-internal module. It provides 32 32-bit memory-mapped interface
registers that can be used to communicate with any arbitrary custom design logic. The intentions of this
registers that can be used to communicate with any arbitrary custom design logic. The intentions of this
subsystem is to provide a simple base, where the user can concentrate on implementing the actual design logic
subsystem is to provide a simple base, where the user can concentrate on implementing the actual design logic
rather than taking care of the communication between the CPU/software and the design logic. The interface
rather than taking care of the communication between the CPU/software and the design logic. The interface
registers are already allocated within the processor's address space and are supported by the software framework
registers are already allocated within the processor's address space and are supported by the software framework
via low-level hardware access mechanisms. Additionally, the CFS provides a direct pre-defined interrupt channel to
via low-level hardware access mechanisms. Additionally, the CFS provides a direct pre-defined interrupt channel to
the CPU, which is also supported by the _NEORV32 runtime environment_.
the CPU, which is also supported by the NEORV32 runtime environment.
 
 
 
 
 
 
 
 
// ####################################################################################################################
// ####################################################################################################################
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The http://vunit.github.io/verification_components/user_guide.html[Verification Component Library] uses those features
The http://vunit.github.io/verification_components/user_guide.html[Verification Component Library] uses those features
for abstracting away bit-toggling when verifying standard interfaces such as Wishbone, AXI, Avalon, UARTs, etc.
for abstracting away bit-toggling when verifying standard interfaces such as Wishbone, AXI, Avalon, UARTs, etc.
 
 
Testbench sources in `sim` (such as `sim/neorv32_tb.vhd` and `sim/uart_rx*.vhd`) use VUnit's VHDL libraries for testing
Testbench sources in `sim` (such as `sim/neorv32_tb.vhd` and `sim/uart_rx*.vhd`) use VUnit's VHDL libraries for testing
NEORV32 and peripherals.
NEORV32 and peripherals.
The entrypoint for executing the tests is `sim/run.py`.
The entry-point for executing the tests is `sim/run.py`.
 
 
[source, bash]
[source, bash]
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# ./sim/run.py -l
# ./sim/run.py -l
neorv32.neorv32_tb.all
neorv32.neorv32_tb.all

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