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This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
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This folder contains the core VHDL files for the NEORV32 CPU and the NEORV32 Processor.
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When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a
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When creating a new synthesis/simulation project make sure that all `*.vhd` files from this folder are added to a
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*new design library* called `neorv32`.
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*new design library* called `neorv32`.
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:warning: The sub-folder [`core/mem`](https://github.com/stnolting/neorv32/tree/master/rtl/core/mem)
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contains the _platform-agnostic_ VHDL architectures of the processor-internal memories.
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You can _replace_ inclusion of these files by platform-optimized memory architectures.
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### [`processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates`)
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### [`processor_templates`](https://github.com/stnolting/neorv32/tree/master/rtl/processor_templates`)
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Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
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Contains pre-configured "SoC" templates that instantiate the processor's top entity from `core`.
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These templates can be instantiated directly within a FPGA-specific board wrapper.
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These templates can be instantiated directly within a FPGA-specific board wrapper.
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