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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> #
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-- # << NEORV32 - Bus Keeper (BUSKEEPER) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This unit monitors the processor-internal bus. If the accessed module does not respond within #
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-- # This unit monitors the processor-internal bus. If the accessed module does not respond within #
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-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR #
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-- # the defined number of cycles (VHDL package: max_proc_int_response_time_c) or issues an ERROR #
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-- # conditions the BUS KEEPER asserts the error signal to inform the CPU. #
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-- # condition, the BUS KEEPER asserts the error signal to inform the CPU. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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-- bus monitoring --
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-- bus monitoring --
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_addr_i : in std_ulogic_vector(31 downto 0); -- address
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bus_rden_i : in std_ulogic; -- read enable
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bus_rden_i : in std_ulogic; -- read enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_wren_i : in std_ulogic; -- write enable
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_ack_i : in std_ulogic; -- transfer acknowledge from bus system
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bus_err_i : in std_ulogic; -- transfer error from bus system
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bus_err_i : in std_ulogic; -- transfer error from bus system
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bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
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bus_tmo_i : in std_ulogic; -- transfer timeout (external interface)
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bus_ext_i : in std_ulogic -- external bus access
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bus_ext_i : in std_ulogic; -- external bus access
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bus_xip_i : in std_ulogic -- pending XIP access
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);
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);
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end neorv32_bus_keeper;
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end neorv32_bus_keeper;
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architecture neorv32_bus_keeper_rtl of neorv32_bus_keeper is
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architecture neorv32_bus_keeper_rtl of neorv32_bus_keeper is
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-- IO space: module base address --
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(buskeeper_size_c); -- low address boundary bit
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-- Control register --
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-- Control register --
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constant ctrl_err_type_c : natural := 0; -- r/-: error type: 0=device error, 1=access timeout
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constant ctrl_err_type_c : natural := 0; -- r/-: error type LSB: 0=device error, 1=access timeout
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constant ctrl_nul_check_en_c : natural := 16; -- r/w: enable NULL address check
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constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero
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constant ctrl_err_flag_c : natural := 31; -- r/c: bus error encountered, sticky; cleared by writing zero
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--
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signal ctrl_null_check_en : std_ulogic;
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-- error codes --
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constant err_device_c : std_ulogic := '0'; -- device access error
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constant err_timeout_c : std_ulogic := '1'; -- timeout error
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-- sticky error flags --
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-- sticky error flags --
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signal err_flag : std_ulogic;
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signal err_flag : std_ulogic;
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signal err_type : std_ulogic;
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signal err_type : std_ulogic;
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-- NULL address check --
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signal null_check : std_ulogic;
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal wren : std_ulogic; -- word write enable
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signal wren : std_ulogic; -- word write enable
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signal rden : std_ulogic; -- read enable
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signal rden : std_ulogic; -- read enable
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rden <= acc_en and rden_i;
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rden <= acc_en and rden_i;
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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rw_access: process(clk_i)
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rw_access: process(rstn_i, clk_i)
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begin
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begin
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if rising_edge(clk_i) then
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if (rstn_i = '0') then
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ack_o <= '-';
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data_o <= (others => '-');
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ctrl_null_check_en <= '0'; -- required
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err_flag <= '0'; -- required
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err_type <= '0';
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elsif rising_edge(clk_i) then
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-- bus handshake --
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-- bus handshake --
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ack_o <= wren or rden;
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ack_o <= wren or rden;
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-- write access --
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if (wren = '1') then
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ctrl_null_check_en <= data_i(ctrl_nul_check_en_c);
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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data_o(ctrl_err_type_c) <= err_type;
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data_o(ctrl_err_type_c) <= err_type;
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data_o(ctrl_nul_check_en_c) <= ctrl_null_check_en;
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data_o(ctrl_err_flag_c) <= err_flag;
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data_o(ctrl_err_flag_c) <= err_flag;
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end if;
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end if;
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--
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--
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if (control.bus_err = '1') then -- sticky error flag
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if (control.bus_err = '1') then -- sticky error flag
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err_flag <= '1';
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err_flag <= '1';
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err_type <= control.err_type;
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err_type <= control.err_type;
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elsif ((wren or rden) = '1') then -- clear on or read or write
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else
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if ((wren or rden) = '1') then -- clear on read or write access
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err_flag <= '0';
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err_flag <= '0';
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err_type <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process rw_access;
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end process rw_access;
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-- Keeper ---------------------------------------------------------------------------------
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-- Keeper ---------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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keeper_control: process(rstn_i, clk_i)
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keeper_control: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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control.pending <= '0';
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control.pending <= '0'; -- required
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control.bus_err <= '0';
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control.bus_err <= '0'; -- required
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control.err_type <= def_rst_val_c;
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control.err_type <= '-';
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control.timeout <= (others => def_rst_val_c);
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control.timeout <= (others => '-');
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- defaults --
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-- defaults --
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control.bus_err <= '0';
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control.bus_err <= '0';
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-- access monitor: IDLE --
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-- access monitor: IDLE --
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if (control.pending = '0') then
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if (control.pending = '0') then
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control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)+1));
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control.timeout <= std_ulogic_vector(to_unsigned(max_proc_int_response_time_c, index_size_f(max_proc_int_response_time_c)+1));
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if (bus_rden_i = '1') or (bus_wren_i = '1') then
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if (bus_rden_i = '1') or (bus_wren_i = '1') then
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control.pending <= '1';
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control.pending <= '1';
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if (null_check = '1') then -- invalid access to NULL address
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control.bus_err <= '1';
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end if;
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end if;
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end if;
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-- access monitor: PENDING --
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-- access monitor: PENDING --
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else
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else
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control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer
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control.timeout <= std_ulogic_vector(unsigned(control.timeout) - 1); -- countdown timer
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if (bus_err_i = '1') then -- error termination by bus system
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if (bus_err_i = '1') or (control.bus_err = '1') then -- error termination by bus system
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control.err_type <= '0'; -- device error
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control.err_type <= err_device_c; -- device error
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control.bus_err <= '1';
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control.bus_err <= '1';
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control.pending <= '0';
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control.pending <= '0';
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elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0')) or -- internal access timeout
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elsif ((or_reduce_f(control.timeout) = '0') and (bus_ext_i = '0') and (bus_xip_i = '0')) or -- valid internal access timeout
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(bus_tmo_i = '1') then -- external access timeout
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(bus_tmo_i = '1') then -- external access timeout
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control.err_type <= '1'; -- timeout error
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control.err_type <= err_timeout_c; -- timeout error
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control.bus_err <= '1';
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control.bus_err <= '1';
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control.pending <= '0';
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control.pending <= '0';
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elsif (bus_ack_i = '1') then -- normal termination by bus system
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elsif (bus_ack_i = '1') then -- normal termination by bus system
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control.err_type <= '0'; -- don't care
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control.err_type <= '0'; -- don't care
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control.bus_err <= '0';
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control.bus_err <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process keeper_control;
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end process keeper_control;
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-- NULL address check --
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null_check <= '1' when (ctrl_null_check_en = '1') and (or_reduce_f(addr_i) = '0') else '0';
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-- signal bus error to CPU --
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-- signal bus error to CPU --
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err_o <= control.bus_err;
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err_o <= control.bus_err;
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end neorv32_bus_keeper_rtl;
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end neorv32_bus_keeper_rtl;
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