Line 70... |
Line 70... |
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_re_i : in std_ulogic; -- read enable
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
cb_bus_err_o : out std_ulogic; -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
|
p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
Line 186... |
Line 187... |
-- arbiter defaults --
|
-- arbiter defaults --
|
arbiter.state_nxt <= arbiter.state;
|
arbiter.state_nxt <= arbiter.state;
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
arbiter.we_trig <= '0';
|
arbiter.we_trig <= '0';
|
arbiter.re_trig <= '0';
|
arbiter.re_trig <= '0';
|
|
--
|
|
p_bus_src_o <= '0';
|
|
|
-- state machine --
|
-- state machine --
|
case arbiter.state is
|
case arbiter.state is
|
|
|
when IDLE => -- Controller a has full bus access
|
when IDLE => -- Controller a has full bus access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
p_bus_src_o <= '0'; -- access from port A
|
if (ca_req_current = '1') then -- current request?
|
if (ca_req_current = '1') then -- current request?
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
arbiter.state_nxt <= BUSY;
|
arbiter.state_nxt <= BUSY;
|
elsif (ca_req_buffered = '1') then -- buffered request?
|
elsif (ca_req_buffered = '1') then -- buffered request?
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
Line 208... |
Line 212... |
arbiter.state_nxt <= RETIRE_SWITCHED;
|
arbiter.state_nxt <= RETIRE_SWITCHED;
|
end if;
|
end if;
|
|
|
when BUSY => -- transaction in progress
|
when BUSY => -- transaction in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
p_bus_src_o <= '0'; -- access from port A
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
if (ca_bus_cancel_i = '1') or -- controller cancels access
|
if (ca_bus_cancel_i = '1') or -- controller cancels access
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
(p_bus_ack_i = '1') then -- normal termination
|
(p_bus_ack_i = '1') then -- normal termination
|
arbiter.state_nxt <= IDLE;
|
arbiter.state_nxt <= IDLE;
|
end if;
|
end if;
|
|
|
when RETIRE => -- retire pending access
|
when RETIRE => -- retire pending access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
p_bus_src_o <= '0'; -- access from port A
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
if (PORT_CA_READ_ONLY = false) then
|
if (PORT_CA_READ_ONLY = false) then
|
arbiter.we_trig <= ca_wr_req_buf;
|
arbiter.we_trig <= ca_wr_req_buf;
|
end if;
|
end if;
|
arbiter.re_trig <= ca_rd_req_buf;
|
arbiter.re_trig <= ca_rd_req_buf;
|
arbiter.state_nxt <= BUSY;
|
arbiter.state_nxt <= BUSY;
|
|
|
when BUSY_SWITCHED => -- switched transaction in progress
|
when BUSY_SWITCHED => -- switched transaction in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
p_bus_src_o <= '1'; -- access from port B
|
arbiter.bus_sel <= '1';
|
arbiter.bus_sel <= '1';
|
if (cb_bus_cancel_i = '1') or -- controller cancels access
|
if (cb_bus_cancel_i = '1') or -- controller cancels access
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
(p_bus_ack_i = '1') then -- normal termination
|
(p_bus_ack_i = '1') then -- normal termination
|
arbiter.state_nxt <= IDLE;
|
arbiter.state_nxt <= IDLE;
|
end if;
|
end if;
|
|
|
when RETIRE_SWITCHED => -- retire pending switched access
|
when RETIRE_SWITCHED => -- retire pending switched access
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
|
p_bus_src_o <= '1'; -- access from port B
|
arbiter.bus_sel <= '1';
|
arbiter.bus_sel <= '1';
|
if (PORT_CB_READ_ONLY = false) then
|
if (PORT_CB_READ_ONLY = false) then
|
arbiter.we_trig <= cb_wr_req_buf;
|
arbiter.we_trig <= cb_wr_req_buf;
|
end if;
|
end if;
|
arbiter.re_trig <= cb_rd_req_buf;
|
arbiter.re_trig <= cb_rd_req_buf;
|