| Line 4... |
Line 4... |
-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port #
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-- # Allows to access a single peripheral bus ("p_bus") by two controller busses. Controller port #
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-- # A ("ca_bus") has priority over controller port B ("cb_bus"). #
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-- # A ("ca_bus") has priority over controller port B ("cb_bus"). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 88... |
Line 88... |
);
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);
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end neorv32_busswitch;
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end neorv32_busswitch;
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|
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architecture neorv32_busswitch_rtl of neorv32_busswitch is
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architecture neorv32_busswitch_rtl of neorv32_busswitch is
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|
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-- access buffer --
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signal ca_rd_req_buf : std_ulogic;
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signal ca_wr_req_buf : std_ulogic;
|
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signal cb_rd_req_buf : std_ulogic;
|
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signal cb_wr_req_buf : std_ulogic;
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|
|
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-- access requests --
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-- access requests --
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signal ca_req_current : std_ulogic;
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signal ca_rd_req_buf, ca_wr_req_buf : std_ulogic;
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signal cb_req_current : std_ulogic;
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signal cb_rd_req_buf, cb_wr_req_buf : std_ulogic;
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signal ca_req_buffered : std_ulogic;
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signal ca_req_current, ca_req_buffered : std_ulogic;
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signal cb_req_buffered : std_ulogic;
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signal cb_req_current, cb_req_buffered : std_ulogic;
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|
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-- internal bus lines --
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-- internal bus lines --
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signal ca_bus_ack : std_ulogic;
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signal ca_bus_ack, cb_bus_ack : std_ulogic;
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signal cb_bus_ack : std_ulogic;
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signal ca_bus_err, cb_bus_err : std_ulogic;
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signal ca_bus_err : std_ulogic;
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signal p_bus_we, p_bus_re : std_ulogic;
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signal cb_bus_err : std_ulogic;
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signal p_bus_we : std_ulogic;
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signal p_bus_re : std_ulogic;
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|
|
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-- access arbiter --
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-- access arbiter --
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type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
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type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
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type arbiter_t is record
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type arbiter_t is record
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state : arbiter_state_t;
|
state : arbiter_state_t;
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| Line 240... |
Line 231... |
p_bus_src_o <= '1'; -- access from port B
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.bus_sel <= '1';
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if (cb_bus_cancel_i = '1') or -- controller cancels access
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if (cb_bus_cancel_i = '1') or -- controller cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_err_i = '1') or -- peripheral cancels access
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(p_bus_ack_i = '1') then -- normal termination
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(p_bus_ack_i = '1') then -- normal termination
|
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if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
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arbiter.state_nxt <= RETIRE;
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else
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arbiter.state_nxt <= IDLE;
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
|
|
end if;
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|
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when RETIRE_SWITCHED => -- retire pending switched access
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when RETIRE_SWITCHED => -- retire pending switched access
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-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
p_bus_src_o <= '1'; -- access from port B
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.bus_sel <= '1';
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