| Line 56... |
Line 56... |
ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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ca_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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ca_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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ca_bus_we_i : in std_ulogic; -- write enable
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ca_bus_we_i : in std_ulogic; -- write enable
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ca_bus_re_i : in std_ulogic; -- read enable
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ca_bus_re_i : in std_ulogic; -- read enable
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ca_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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ca_bus_lock_i : in std_ulogic; -- exclusive access request
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ca_bus_excl_i : in std_ulogic; -- exclusive access
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ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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ca_bus_err_o : out std_ulogic; -- bus transfer error
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ca_bus_err_o : out std_ulogic; -- bus transfer error
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-- controller interface b --
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-- controller interface b --
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cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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cb_bus_addr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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cb_bus_rdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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cb_bus_wdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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cb_bus_we_i : in std_ulogic; -- write enable
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cb_bus_we_i : in std_ulogic; -- write enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_cancel_i : in std_ulogic; -- cancel current bus transaction
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cb_bus_lock_i : in std_ulogic; -- exclusive access request
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cb_bus_excl_i : in std_ulogic; -- exclusive access
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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-- peripheral bus --
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-- peripheral bus --
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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p_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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p_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_we_o : out std_ulogic; -- write enable
|
p_bus_re_o : out std_ulogic; -- read enable
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p_bus_re_o : out std_ulogic; -- read enable
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p_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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p_bus_lock_o : out std_ulogic; -- exclusive access request
|
p_bus_excl_o : out std_ulogic; -- exclusive access
|
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
p_bus_err_i : in std_ulogic -- bus transfer error
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p_bus_err_i : in std_ulogic -- bus transfer error
|
);
|
);
|
end neorv32_busswitch;
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end neorv32_busswitch;
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| Line 127... |
Line 124... |
|
|
-- controller A requests --
|
-- controller A requests --
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if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle
|
if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle
|
ca_rd_req_buf <= ca_bus_re_i;
|
ca_rd_req_buf <= ca_bus_re_i;
|
ca_wr_req_buf <= ca_bus_we_i;
|
ca_wr_req_buf <= ca_bus_we_i;
|
elsif (ca_bus_cancel_i = '1') or -- controller cancels access
|
elsif (ca_bus_err = '1') or -- error termination
|
(ca_bus_err = '1') or -- peripheral cancels access
|
|
(ca_bus_ack = '1') then -- normal termination
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(ca_bus_ack = '1') then -- normal termination
|
ca_rd_req_buf <= '0';
|
ca_rd_req_buf <= '0';
|
ca_wr_req_buf <= '0';
|
ca_wr_req_buf <= '0';
|
end if;
|
end if;
|
|
|
-- controller B requests --
|
-- controller B requests --
|
if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then
|
if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then
|
cb_rd_req_buf <= cb_bus_re_i;
|
cb_rd_req_buf <= cb_bus_re_i;
|
cb_wr_req_buf <= cb_bus_we_i;
|
cb_wr_req_buf <= cb_bus_we_i;
|
elsif (cb_bus_cancel_i = '1') or -- controller cancels access
|
elsif (cb_bus_err = '1') or -- error termination
|
(cb_bus_err = '1') or -- peripheral cancels access
|
|
(cb_bus_ack = '1') then -- normal termination
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(cb_bus_ack = '1') then -- normal termination
|
cb_rd_req_buf <= '0';
|
cb_rd_req_buf <= '0';
|
cb_wr_req_buf <= '0';
|
cb_wr_req_buf <= '0';
|
end if;
|
end if;
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|
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| Line 173... |
Line 168... |
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|
|
-- Peripheral Bus Arbiter -----------------------------------------------------------------
|
-- Peripheral Bus Arbiter -----------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
|
arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
|
ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf,
|
ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i)
|
ca_bus_cancel_i, cb_bus_cancel_i, p_bus_ack_i, p_bus_err_i)
|
|
begin
|
begin
|
-- arbiter defaults --
|
-- arbiter defaults --
|
arbiter.state_nxt <= arbiter.state;
|
arbiter.state_nxt <= arbiter.state;
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
arbiter.we_trig <= '0';
|
arbiter.we_trig <= '0';
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| Line 208... |
Line 202... |
|
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when BUSY => -- transaction in progress
|
when BUSY => -- transaction in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
p_bus_src_o <= '0'; -- access from port A
|
p_bus_src_o <= '0'; -- access from port A
|
arbiter.bus_sel <= '0';
|
arbiter.bus_sel <= '0';
|
if (ca_bus_cancel_i = '1') or -- controller cancels access
|
if (p_bus_err_i = '1') or -- error termination
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
|
(p_bus_ack_i = '1') then -- normal termination
|
(p_bus_ack_i = '1') then -- normal termination
|
arbiter.state_nxt <= IDLE;
|
arbiter.state_nxt <= IDLE;
|
end if;
|
end if;
|
|
|
when RETIRE => -- retire pending access
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when RETIRE => -- retire pending access
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| Line 228... |
Line 221... |
|
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when BUSY_SWITCHED => -- switched transaction in progress
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when BUSY_SWITCHED => -- switched transaction in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
p_bus_src_o <= '1'; -- access from port B
|
p_bus_src_o <= '1'; -- access from port B
|
arbiter.bus_sel <= '1';
|
arbiter.bus_sel <= '1';
|
if (cb_bus_cancel_i = '1') or -- controller cancels access
|
if (p_bus_err_i = '1') or -- error termination
|
(p_bus_err_i = '1') or -- peripheral cancels access
|
|
(p_bus_ack_i = '1') then -- normal termination
|
(p_bus_ack_i = '1') then -- normal termination
|
if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
|
if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
|
arbiter.state_nxt <= RETIRE;
|
arbiter.state_nxt <= RETIRE;
|
else
|
else
|
arbiter.state_nxt <= IDLE;
|
arbiter.state_nxt <= IDLE;
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| Line 261... |
Line 253... |
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
|
ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
|
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
|
p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
|
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
|
ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
|
p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
|
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
|
p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
|
p_bus_cancel_o <= ca_bus_cancel_i when (arbiter.bus_sel = '0') else cb_bus_cancel_i;
|
|
p_bus_we_o <= (p_bus_we or arbiter.we_trig);
|
p_bus_we_o <= (p_bus_we or arbiter.we_trig);
|
p_bus_re_o <= (p_bus_re or arbiter.re_trig);
|
p_bus_re_o <= (p_bus_re or arbiter.re_trig);
|
p_bus_excl_o <= ca_bus_excl_i or cb_bus_excl_i;
|
p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i;
|
|
|
ca_bus_rdata_o <= p_bus_rdata_i;
|
ca_bus_rdata_o <= p_bus_rdata_i;
|
cb_bus_rdata_o <= p_bus_rdata_i;
|
cb_bus_rdata_o <= p_bus_rdata_i;
|
|
|
ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
|
ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
|
