| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Bus Switch >> #
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-- # << NEORV32 - Bus Switch >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Allows to access a single peripheral bus ("p_bus") by two controller buses. Controller port A #
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-- # Allows to access a single peripheral bus ("p_bus") by two controller ports. Controller port A #
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-- # ("ca_bus") has priority over controller port B ("cb_bus"). #
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-- # ("ca_bus") has priority over controller port B ("cb_bus"). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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| Line 97... |
Line 97... |
signal ca_bus_ack, cb_bus_ack : std_ulogic;
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signal ca_bus_ack, cb_bus_ack : std_ulogic;
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signal ca_bus_err, cb_bus_err : std_ulogic;
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signal ca_bus_err, cb_bus_err : std_ulogic;
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signal p_bus_we, p_bus_re : std_ulogic;
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signal p_bus_we, p_bus_re : std_ulogic;
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-- access arbiter --
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-- access arbiter --
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type arbiter_state_t is (IDLE, BUSY, RETIRE, BUSY_SWITCHED, RETIRE_SWITCHED);
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type arbiter_state_t is (IDLE, A_BUSY, A_RETIRE, B_BUSY, B_RETIRE);
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type arbiter_t is record
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type arbiter_t is record
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state : arbiter_state_t;
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state : arbiter_state_t;
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state_nxt : arbiter_state_t;
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state_nxt : arbiter_state_t;
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bus_sel : std_ulogic;
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bus_sel : std_ulogic;
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re_trig : std_ulogic;
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re_trig : std_ulogic;
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| Line 109... |
Line 109... |
end record;
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end record;
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signal arbiter : arbiter_t;
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signal arbiter : arbiter_t;
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begin
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begin
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-- Access Buffer --------------------------------------------------------------------------
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-- Access Arbiter -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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access_buffer: process(rstn_i, clk_i)
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arbiter_sync: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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arbiter.state <= IDLE;
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ca_rd_req_buf <= '0';
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ca_rd_req_buf <= '0';
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ca_wr_req_buf <= '0';
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ca_wr_req_buf <= '0';
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cb_rd_req_buf <= '0';
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cb_rd_req_buf <= '0';
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cb_wr_req_buf <= '0';
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cb_wr_req_buf <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- arbiter --
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arbiter.state <= arbiter.state_nxt;
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-- controller A requests --
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-- controller A requests --
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if (ca_rd_req_buf = '0') and (ca_wr_req_buf = '0') then -- idle
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ca_rd_req_buf <= (ca_rd_req_buf or ca_bus_re_i) and (not (ca_bus_err or ca_bus_ack));
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ca_rd_req_buf <= ca_bus_re_i;
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ca_wr_req_buf <= (ca_wr_req_buf or ca_bus_we_i) and (not (ca_bus_err or ca_bus_ack)) and (not bool_to_ulogic_f(PORT_CA_READ_ONLY));
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ca_wr_req_buf <= ca_bus_we_i;
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elsif (ca_bus_err = '1') or -- error termination
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(ca_bus_ack = '1') then -- normal termination
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ca_rd_req_buf <= '0';
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ca_wr_req_buf <= '0';
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end if;
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-- controller B requests --
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-- controller B requests --
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if (cb_rd_req_buf = '0') and (cb_wr_req_buf = '0') then
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cb_rd_req_buf <= (cb_rd_req_buf or cb_bus_re_i) and (not (cb_bus_err or cb_bus_ack));
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cb_rd_req_buf <= cb_bus_re_i;
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cb_wr_req_buf <= (cb_wr_req_buf or cb_bus_we_i) and (not (cb_bus_err or cb_bus_ack)) and (not bool_to_ulogic_f(PORT_CB_READ_ONLY));
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cb_wr_req_buf <= cb_bus_we_i;
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elsif (cb_bus_err = '1') or -- error termination
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(cb_bus_ack = '1') then -- normal termination
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cb_rd_req_buf <= '0';
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cb_wr_req_buf <= '0';
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end if;
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end if;
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end if;
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end process access_buffer;
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end process arbiter_sync;
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-- any current requests? --
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-- any current requests? --
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ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i;
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ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i;
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cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i;
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cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i;
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-- any buffered requests? --
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-- any buffered requests? --
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ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf;
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ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf;
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cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf;
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cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf;
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-- Access Arbiter Sync --------------------------------------------------------------------
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-- Bus Arbiter ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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arbiter_sync: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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arbiter.state <= IDLE;
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elsif rising_edge(clk_i) then
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arbiter.state <= arbiter.state_nxt;
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end if;
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end process arbiter_sync;
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-- Peripheral Bus Arbiter -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
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arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
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ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i)
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ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i)
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begin
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begin
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-- arbiter defaults --
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-- arbiter defaults --
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| Line 178... |
Line 154... |
arbiter.re_trig <= '0';
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arbiter.re_trig <= '0';
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-- state machine --
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-- state machine --
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case arbiter.state is
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case arbiter.state is
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when IDLE => -- Controller a has full bus access
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when IDLE => -- port A or B access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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if (ca_req_current = '1') then -- current request from controller A?
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if (ca_req_current = '1') then -- current request?
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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arbiter.state_nxt <= A_BUSY;
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arbiter.state_nxt <= BUSY;
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elsif (ca_req_buffered = '1') then -- buffered request from controller A?
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elsif (ca_req_buffered = '1') then -- buffered request?
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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arbiter.state_nxt <= A_RETIRE;
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arbiter.state_nxt <= RETIRE;
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elsif (cb_req_current = '1') then -- buffered request from controller B?
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elsif (cb_req_current = '1') then -- current request from controller b?
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.state_nxt <= B_BUSY;
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arbiter.state_nxt <= BUSY_SWITCHED;
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elsif (cb_req_buffered = '1') then -- current request from controller B?
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elsif (cb_req_buffered = '1') then -- buffered request from controller b?
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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arbiter.state_nxt <= B_RETIRE;
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arbiter.state_nxt <= RETIRE_SWITCHED;
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end if;
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end if;
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when BUSY => -- transaction in progress
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when A_BUSY => -- port A pending access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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if (p_bus_err_i = '1') or (p_bus_ack_i = '1') then -- termination
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if (p_bus_err_i = '1') or -- error termination
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(p_bus_ack_i = '1') then -- normal termination
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arbiter.state_nxt <= IDLE;
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
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when RETIRE => -- retire pending access
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when A_RETIRE => -- port A trigger buffered access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '0'; -- access from port A
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.bus_sel <= '0';
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if (PORT_CA_READ_ONLY = false) then
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arbiter.we_trig <= ca_wr_req_buf;
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arbiter.we_trig <= ca_wr_req_buf;
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end if;
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arbiter.re_trig <= ca_rd_req_buf;
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arbiter.re_trig <= ca_rd_req_buf;
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arbiter.state_nxt <= BUSY;
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arbiter.state_nxt <= A_BUSY;
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when BUSY_SWITCHED => -- switched transaction in progress
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when B_BUSY => -- port B pending access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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if (p_bus_err_i = '1') or (p_bus_ack_i = '1') then -- termination
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if (p_bus_err_i = '1') or -- error termination
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(p_bus_ack_i = '1') then -- normal termination
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if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
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if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
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arbiter.state_nxt <= RETIRE;
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arbiter.state_nxt <= A_RETIRE;
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else
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else
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arbiter.state_nxt <= IDLE;
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
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end if;
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end if;
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when RETIRE_SWITCHED => -- retire pending switched access
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when B_RETIRE => -- port B trigger buffered access
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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p_bus_src_o <= '1'; -- access from port B
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.bus_sel <= '1';
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if (PORT_CB_READ_ONLY = false) then
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arbiter.we_trig <= cb_wr_req_buf;
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arbiter.we_trig <= cb_wr_req_buf;
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end if;
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arbiter.re_trig <= cb_rd_req_buf;
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arbiter.re_trig <= cb_rd_req_buf;
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arbiter.state_nxt <= BUSY_SWITCHED;
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arbiter.state_nxt <= B_BUSY;
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end case;
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end case;
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end process arbiter_comb;
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end process arbiter_comb;
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-- Peripheral Bus Switch ------------------------------------------------------------------
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-- Peripheral Bus Switch ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i;
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p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i;
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p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else
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p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else
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ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else
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ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
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ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
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p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
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p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else
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ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
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ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
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ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
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p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
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p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
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p_bus_we_o <= (p_bus_we or arbiter.we_trig);
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p_bus_we_o <= (p_bus_we or arbiter.we_trig);
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p_bus_re_o <= (p_bus_re or arbiter.re_trig);
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p_bus_re_o <= (p_bus_re or arbiter.re_trig);
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p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i;
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p_bus_lock_o <= ca_bus_lock_i or cb_bus_lock_i;
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p_bus_src_o <= arbiter.bus_sel;
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|
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ca_bus_rdata_o <= p_bus_rdata_i;
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ca_bus_rdata_o <= p_bus_rdata_i;
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cb_bus_rdata_o <= p_bus_rdata_i;
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cb_bus_rdata_o <= p_bus_rdata_i;
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|
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ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
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ca_bus_ack <= p_bus_ack_i and (not arbiter.bus_sel);
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