| Line 122... |
Line 122... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low.
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-- The CFS can be reset using the global rstn_i signal. This signal should be used as asynchronous reset and is active-low.
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-- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset.
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-- Note that rstn_i can be asserted by an external reset and also by a watchdog-cause reset.
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--
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--
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-- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO
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-- Most default peripheral devices of the NEORV32 do NOT use a dedicated reset at all. Instead, these units are reset by writing ZERO
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-- to a specific "control register" located right at the beginning of the devices's address space (so this register is cleared at first).
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-- to a specific "control register" located right at the beginning of the device's address space (so this register is cleared at first).
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-- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS.
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-- The crt0 start-up code write ZERO to every single address in the processor's IO space - including the CFS.
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-- Make sure that this clearing does not cause any unintended actions in the CFS.
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-- Make sure that this clearing does not cause any unintended actions in the CFS.
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-- Clock System ---------------------------------------------------------------------------
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-- Clock System ---------------------------------------------------------------------------
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| Line 208... |
Line 208... |
-- ack_o <= rden; -- use this construct if your CFS is read-only
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-- ack_o <= rden; -- use this construct if your CFS is read-only
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-- ack_o <= wren; -- use this construct if your CFS is write-only
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-- ack_o <= wren; -- use this construct if your CFS is write-only
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-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
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-- ack_o <= ... -- or define the ACK by yourself (example: some registers are read-only, some others can only be written, ...)
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-- write access --
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-- write access --
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for i in 0 to 3 loop
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if (wren = '1') then -- word-wide write-access only!
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if (wren = '1') then -- word-wide write-access only!
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case addr is -- make sure to use the internal 'addr' signal for the read/write interface
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case addr is -- make sure to use the internal "addr" signal for the read/write interface
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when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
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when cfs_reg0_addr_c => cfs_reg_wr(0) <= data_i; -- for example: control register
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when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
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when cfs_reg1_addr_c => cfs_reg_wr(1) <= data_i; -- for example: data in/out fifo
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when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
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when cfs_reg2_addr_c => cfs_reg_wr(2) <= data_i; -- for example: command fifo
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when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
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when cfs_reg3_addr_c => cfs_reg_wr(3) <= data_i; -- for example: status register
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when others => NULL;
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when others => NULL;
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end case;
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end case;
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end if;
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end if;
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end loop; -- i
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-- read access --
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-- read access --
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data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
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data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
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if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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if (rden = '1') then -- the read access is always a full 32-bit word wide; if required, the byte/half-word select/masking is done in the CPU
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case addr is -- make sure to use the internal 'addr' signal for the read/write interface
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case addr is -- make sure to use the internal 'addr' signal for the read/write interface
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