| Line 64... |
Line 64... |
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
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clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
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-- CPU state --
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-- CPU state --
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sleep_i : in std_ulogic; -- set if cpu is in sleep mode
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sleep_i : in std_ulogic; -- set if cpu is in sleep mode
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-- interrupt --
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-- interrupt --
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irq_o : out std_ulogic; -- interrupt request
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irq_o : out std_ulogic; -- interrupt request
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irq_ack_i : in std_ulogic; -- interrupt acknowledge
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-- custom io (conduits) --
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-- custom io (conduits) --
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cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs
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cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs
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cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs
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);
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);
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end neorv32_cfs;
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end neorv32_cfs;
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| Line 155... |
Line 154... |
-- end if;
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-- end if;
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-- end if;
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-- end if;
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--
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--
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks generated by the
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks generated by the
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-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- The CFS cannot ensure to deactive the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might still keep the generator activated.
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-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.
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-- Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to reduce dynamic power consumption.
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|
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clkgen_en_o <= '0'; -- not used for this minimal example
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clkgen_en_o <= '0'; -- not used for this minimal example
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| Line 188... |
Line 187... |
-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)
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-- modules of the NEORV32 can only be written in full word mode (32-bit). Any other write access (half-word or byte)
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-- will trigger a store bus access fault exception.
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-- will trigger a store bus access fault exception.
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--
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--
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-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide
|
-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- a <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a <command register>
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-- for issueing commands and a <status register> for status information.
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-- for issuing commands and a <status register> for status information.
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--
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--
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o signal (or even later
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-- if the module needs additional time; the maximumx latency until an unacknwoledged access will trigger a bus exception is defined via the package's
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-- if the module needs additional time; the maximum latency until an unacknowledged access will trigger a bus exception is defined via the package's
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-- gloabl "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception.
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-- global "bus_timeout_c" constant). If no ACK is generated, the bus access will time out and cause a store bus access fault exception.
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|
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge.
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-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
|
-- This example only implements four physical r/w register (the four lowest CF register). The remaining addresses of the CFS are not
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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-- associated with any writable or readable register - an access to those is simply ignored but still acknowledged.
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