| Line 74... |
Line 74... |
);
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);
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end neorv32_cfs;
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end neorv32_cfs;
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architecture neorv32_cfs_rtl of neorv32_cfs is
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architecture neorv32_cfs_rtl of neorv32_cfs is
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-- IO space: module base address (DO NOT MODIFY!) --
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-- IO space: module base address --
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-- WARNING: Do not modify the CFS base address or the CFS' occupied address
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-- space as this might cause access collisions with other processor modules.
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(cfs_size_c); -- low address boundary bit
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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| Line 93... |
Line 95... |
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- This logic is required to handle the CPU accesses.
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-- This logic is required to handle the CPU accesses - DO NOT MODIFY!
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-- DO NOT MODIFY this unless you really know what you are doing.
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = cfs_base_c(hi_abb_c downto lo_abb_c)) else '0';
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addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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addr <= cfs_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i; -- write accesses always write a full 32-bit word
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wren <= acc_en and wren_i; -- only full-word write accesses are supported
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rden <= acc_en and rden_i; -- read accesses always return a full 32-bit word
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rden <= acc_en and rden_i; -- read accesses always return a full 32-bit word
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-- NOTE: Do not modify the CFS base address or the CFS' occupied address space as this might cause access
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-- collisions with other modules.
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-- CFS Generics ---------------------------------------------------------------------------
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-- CFS Generics ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- In it's default version the CFS provides three configuration generics:
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-- In it's default version the CFS provides three configuration generics:
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-- CFS_IN_SIZE - configures the size (in bits) of the CFS input conduit cfs_in_i
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-- > CFS_IN_SIZE - configures the size (in bits) of the CFS input conduit cfs_in_i
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-- CFS_OUT_SIZE - configures the size (in bits) of the CFS output conduit cfs_out_o
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-- > CFS_OUT_SIZE - configures the size (in bits) of the CFS output conduit cfs_out_o
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-- CFS_CONFIG - is a blank 32-bit generic. It is intended as a "generic conduit" to propagate
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-- > CFS_CONFIG - is a blank 32-bit generic. It is intended as a "generic conduit" to propagate
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-- custom configuration flags from the top entity down to this module.
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-- custom configuration flags from the top entity down to this module.
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-- CFS IOs --------------------------------------------------------------------------------
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-- CFS IOs --------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 139... |
Line 137... |
-- The processor top unit implements a clock generator providing 8 "derived clocks".
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-- The processor top unit implements a clock generator providing 8 "derived clocks".
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-- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals.
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-- Actually, these signals should not be used as direct clock signals, but as *clock enable* signals.
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-- clkgen_i is always synchronous to the main system clock (clk_i).
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-- clkgen_i is always synchronous to the main system clock (clk_i).
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--
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--
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-- The following clock dividers are available:
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-- The following clock dividers are available:
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-- + clkgen_i(clk_div2_c) -> MAIN_CLK/2
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-- > clkgen_i(clk_div2_c) -> MAIN_CLK/2
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-- + clkgen_i(clk_div4_c) -> MAIN_CLK/4
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-- > clkgen_i(clk_div4_c) -> MAIN_CLK/4
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-- + clkgen_i(clk_div8_c) -> MAIN_CLK/8
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-- > clkgen_i(clk_div8_c) -> MAIN_CLK/8
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-- + clkgen_i(clk_div64_c) -> MAIN_CLK/64
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-- > clkgen_i(clk_div64_c) -> MAIN_CLK/64
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-- + clkgen_i(clk_div128_c) -> MAIN_CLK/128
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-- > clkgen_i(clk_div128_c) -> MAIN_CLK/128
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-- + clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
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-- > clkgen_i(clk_div1024_c) -> MAIN_CLK/1024
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-- + clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
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-- > clkgen_i(clk_div2048_c) -> MAIN_CLK/2048
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-- + clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
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-- > clkgen_i(clk_div4096_c) -> MAIN_CLK/4096
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--
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--
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-- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct:
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-- For instance, if you want to drive a clock process at MAIN_CLK/8 clock speed you can use the following construct:
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--
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--
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-- if (rstn_i = '0') then -- async and low-active reset (if required at all)
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-- if (rstn_i = '0') then -- async and low-active reset (if required at all)
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-- ...
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-- ...
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-- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes!
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-- elsif rising_edge(clk_i) then -- always use the main clock for all clock processes
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-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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-- if (clkgen_i(clk_div8_c) = '1') then -- the div8 "clock" is actually a clock enable
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-- ...
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-- ...
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-- end if;
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-- end if;
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-- end if;
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-- end if;
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--
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--
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example the UART) requires the clocks
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-- The clkgen_i input clocks are available when at least one IO/peripheral device (for example UART0) requires the clocks
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-- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- generated by the clock generator. The CFS can enable the clock generator by itself by setting the clkgen_en_o signal high.
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might
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-- The CFS cannot ensure to deactivate the clock generator by setting the clkgen_en_o signal low as other peripherals might
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-- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to
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-- still keep the generator activated. Make sure to deactivate the CFS's clkgen_en_o if no clocks are required in here to
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-- reduce dynamic power consumption.
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-- reduce dynamic power consumption.
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| Line 179... |
Line 177... |
irq_o <= '0'; -- not used for this minimal example
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irq_o <= '0'; -- not used for this minimal example
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-- Read/Write Access ----------------------------------------------------------------------
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-- Read/Write Access ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- Here we are reading/writing from/to the interface registers of the module. Please note that the peripheral/IO modules
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-- Here we are reading/writing from/to the interface registers of the module and generate the CPU access handshake (bus response).
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-- of the NEORV32 can only be written in full word mode (32-bit). Any other write accesses (half-word or byte) will raise
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-- a store bus access fault exception.
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--
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--
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-- The CFS provides up to 32 memory-mapped 32-bit interface register. For instance, these could be used to provide a
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-- The CFS provides up to 32 memory-mapped 32-bit interface registers. For instance, these could be used to provide a
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-- <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a
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-- <control register> for global control of the unit, a <data register> for reading/writing from/to a data FIFO, a
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-- <command register> for issuing commands and a <status register> for status information.
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-- <command register> for issuing commands and a <status register> for status information.
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--
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--
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o
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-- Following the interface protocol, each read or write access has to be acknowledged in the following cycle using the ack_o
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-- signal (or even later if the module needs additional time; exceeding the maximum ACK latency will raise a bus exception).
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-- signal (or even later if the module needs additional time). If no ACK is generated at all, the bus access will time out
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-- If no ACK is generated at all, the bus access will time out and cause a bus access fault exception.
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-- and cause a bus access fault exception.
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--
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--
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-- This module also provides an optional ERROR signal to indicate a faulty access operation (for example when accessing an
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-- This module also provides an optional ERROR signal to indicate a faulty access operation (for example when accessing an
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-- unused, read-only or "locked" CFS register address). This signal may only be set when the module is actually accessed
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-- unused, read-only or "locked" CFS register address). This signal may only be set when the module is actually accessed
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-- and is asserted INSTEAD of the ACK signal. Setting the ERR signal will raise a bus access exception that can be handled
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-- and is set INSTEAD of the ACK signal. Setting the ERR signal will raise a bus access exception with a "Device Error" qualifier
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-- by the application software.
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-- that can be handled by the application software.
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err_o <= '0'; -- Tie to zero if not explicitly used.
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err_o <= '0'; -- Tie to zero if not explicitly used.
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-- Host access: Read and write access to the interface registers + bus transfer acknowledge. This example only implements
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-- four physical r/w register (the four lowest CFS registers). The remaining addresses of the CFS are not associated with
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-- Host access example: Read and write access to the interface registers + bus transfer acknowledge. This example only
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-- any physical registers - any access to those is simply ignored but still acknowledged.
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-- implements four physical r/w register (the four lowest CFS registers). The remaining addresses of the CFS are not associated
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-- with any physical registers - any access to those is simply ignored but still acknowledged. Only full-word write accesses are
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-- supported (and acknowledged) by this example. Sub-word write access will not alter any CFS register state and will cause
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-- a "bus store access" exception (with a "Device Timeout" qualifier as not ACK is generated in that case).
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host_access: process(clk_i)
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host_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then -- synchronous interface for read and write accesses
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if rising_edge(clk_i) then -- synchronous interface for read and write accesses
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-- transfer/access acknowledge --
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-- transfer/access acknowledge --
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ack_o <= rden or wren; -- default: required for the CPU to check the CFS is answering a bus read OR write request;
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-- default: required for the CPU to check the CFS is answering a bus read OR write request;
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-- all r/w accesses (to any cfs_reg) will succeed
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-- all read and write accesses (to any cfs_reg, even if there is no according physical register implemented) will succeed.
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ack_o <= rden or wren;
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-- write access --
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-- write access --
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if (wren = '1') then
|
if (wren = '1') then -- full-word write access, high for one cycle if there is an actual write access
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if (addr = cfs_reg0_addr_c) then -- make sure to use the internal "addr" signal for the read/write interface
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if (addr = cfs_reg0_addr_c) then -- make sure to use the internal "addr" signal for the read/write interface
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cfs_reg_wr(0) <= data_i; -- physical register, for example: control register
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cfs_reg_wr(0) <= data_i; -- some physical register, for example: control register
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end if;
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end if;
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if (addr = cfs_reg1_addr_c) then
|
if (addr = cfs_reg1_addr_c) then
|
cfs_reg_wr(1) <= data_i; -- physical register, for example: data in/out fifo
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cfs_reg_wr(1) <= data_i; -- some physical register, for example: data in/out fifo
|
end if;
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end if;
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if (addr = cfs_reg2_addr_c) then
|
if (addr = cfs_reg2_addr_c) then
|
cfs_reg_wr(2) <= data_i; -- physical register, for example: command fifo
|
cfs_reg_wr(2) <= data_i; -- some physical register, for example: command fifo
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end if;
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end if;
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if (addr = cfs_reg3_addr_c) then
|
if (addr = cfs_reg3_addr_c) then
|
cfs_reg_wr(3) <= data_i; -- physical register, for example: status register
|
cfs_reg_wr(3) <= data_i; -- some physical register, for example: status register
|
end if;
|
end if;
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end if;
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end if;
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|
|
-- read access --
|
-- read access --
|
data_o <= (others => '0'); -- the output has to be zero if there is no actual read access
|
data_o <= (others => '0'); -- the output HAS TO BE ZERO if there is no actual read access
|
if (rden = '1') then -- the read access is always a full 32-bit word wide
|
if (rden = '1') then -- the read access is always 32-bit wide, high for one cycle if there is an actual read access
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case addr is -- make sure to use the internal 'addr' signal for the read/write interface
|
case addr is -- make sure to use the internal 'addr' signal for the read/write interface
|
when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0);
|
when cfs_reg0_addr_c => data_o <= cfs_reg_rd(0);
|
when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1);
|
when cfs_reg1_addr_c => data_o <= cfs_reg_rd(1);
|
when cfs_reg2_addr_c => data_o <= cfs_reg_rd(2);
|
when cfs_reg2_addr_c => data_o <= cfs_reg_rd(2);
|
when cfs_reg3_addr_c => data_o <= cfs_reg_rd(3);
|
when cfs_reg3_addr_c => data_o <= cfs_reg_rd(3);
|
| Line 245... |
Line 245... |
-- CFS Function Core ----------------------------------------------------------------------
|
-- CFS Function Core ----------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
|
-- This is where the actual functionality can be implemented.
|
-- This is where the actual functionality can be implemented.
|
-- The logic below is just a very simple example that transforms data
|
-- The logic below is just a very simple example that transforms data
|
-- from an inpout register into data in an output register.
|
-- from an input register into data in an output register.
|
cfs_core_logic: process(cfs_reg_wr)
|
|
begin
|
|
cfs_reg_rd(0) <= bin_to_gray_f(cfs_reg_wr(0)); -- convert binary to gray code
|
cfs_reg_rd(0) <= bin_to_gray_f(cfs_reg_wr(0)); -- convert binary to gray code
|
cfs_reg_rd(1) <= gray_to_bin_f(cfs_reg_wr(1)); -- convert gray to binary code
|
cfs_reg_rd(1) <= gray_to_bin_f(cfs_reg_wr(1)); -- convert gray to binary code
|
cfs_reg_rd(2) <= bit_rev_f(cfs_reg_wr(2)); -- bit reversal
|
cfs_reg_rd(2) <= bit_rev_f(cfs_reg_wr(2)); -- bit reversal
|
cfs_reg_rd(3) <= bswap32_f(cfs_reg_wr(3)); -- byte swap (endianness conversion)
|
cfs_reg_rd(3) <= bswap32_f(cfs_reg_wr(3)); -- byte swap (endianness conversion)
|
end process cfs_core_logic;
|
|
|
|
|
|
end neorv32_cfs_rtl;
|
end neorv32_cfs_rtl;
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No newline at end of file
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No newline at end of file
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