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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= x"00000000"; -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Memory configuration: External memory interface --
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-- Bus Interface --
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MEM_EXT_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic := '0'; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
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-- instruction bus interface --
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-- instruction bus interface --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic; -- bus transfer error
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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-- data bus interface --
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- external interrupts --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic; -- software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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clic_irq_i : in std_ulogic; -- CLIC interrupt request
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mtime_irq_i : in std_ulogic -- machine timer interrupt
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mtime_irq_i : in std_ulogic := '0'; -- machine timer interrupt
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-- fast interrupts (custom) --
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firq_i : in std_ulogic_vector(3 downto 0) := (others => '0')
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);
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);
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end neorv32_cpu;
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end neorv32_cpu;
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architecture neorv32_cpu_rtl of neorv32_cpu is
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architecture neorv32_cpu_rtl of neorv32_cpu is
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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-- csr interface --
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-- csr interface --
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csr_wdata_i => alu_res, -- CSR write data
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csr_wdata_i => alu_res, -- CSR write data
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- external interrupt --
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-- interrupts (risc-v compliant) --
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msw_irq_i => msw_irq_i, -- software interrupt
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msw_irq_i => msw_irq_i, -- machine software interrupt
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clic_irq_i => clic_irq_i, -- CLIC interrupt request
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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-- fast interrupts (custom) --
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firq_i => firq_i,
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i => time_i, -- current system time
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time_i => time_i, -- current system time
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-- bus access exceptions --
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-- bus access exceptions --
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mar_i => mar, -- memory address register
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mar_i => mar, -- memory address register
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ma_instr_i => ma_instr, -- misaligned instruction address
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ma_instr_i => ma_instr, -- misaligned instruction address
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- Bus Interface Unit ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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generic map (
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generic map (
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT => BUS_TIMEOUT -- cycles after which a valid bus access will timeout
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)
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)
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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