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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Extension Options --
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 8)
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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PMP_GRANULARITY : natural := 14; -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Bus Interface --
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-- Bus Interface --
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_start, cp1_start : std_ulogic;
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-- pmp interface --
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-- pmp interface --
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
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signal priv_mode : std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- data output --
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-- data output --
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cmp_o => alu_cmp, -- comparator status
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cmp_o => alu_cmp, -- comparator status
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add_o => alu_add, -- OPA + OPB
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add_o => alu_add, -- OPA + OPB
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_valid_i => cp1_valid, -- co-processor 1 result valid
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cp1_valid_i => cp1_valid, -- co-processor 1 result valid
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-- status --
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-- status --
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wait_o => alu_wait -- busy due to iterative processing units
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wait_o => alu_wait -- busy due to iterative processing units
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);
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);
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-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
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-- Co-Processor 0: MULDIV Unit ------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_muldiv_inst_true:
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neorv32_cpu_cp_muldiv_inst_true:
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if (CPU_EXTENSION_RISCV_M = true) generate
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if (CPU_EXTENSION_RISCV_M = true) generate
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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generic map (
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FAST_MUL_EN => FAST_MUL_EN -- use DSPs for faster multiplication
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)
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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start_i => cp0_start, -- trigger operation
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp0_data, -- operation result
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res_o => cp0_data, -- operation result
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valid_o => cp0_valid -- data output valid
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valid_o => cp0_valid -- data output valid
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