| Line 130... |
Line 130... |
signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp_opa, cp_opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_start, cp1_start : std_ulogic;
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signal cp0_start, cp1_start : std_ulogic;
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-- pmp interface --
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-- pmp interface --
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| Line 193... |
Line 192... |
bus_d_wait_i => bus_d_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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-- data input --
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-- data input --
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instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => alu_cmp, -- comparator status
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cmp_i => alu_cmp, -- comparator status
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alu_add_i => alu_add, -- ALU.add result
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alu_add_i => alu_add, -- ALU.add result
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alu_res_i => alu_res, -- ALU processing result
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction
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-- csr interface --
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csr_wdata_i => alu_res, -- CSR write data
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i => msw_irq_i, -- machine software interrupt
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msw_irq_i => msw_irq_i, -- machine software interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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| Line 261... |
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-- data input --
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-- data input --
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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pc2_i => curr_pc, -- delayed PC
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pc2_i => curr_pc, -- delayed PC
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imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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csr_i => csr_rdata, -- csr read data
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-- data output --
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-- data output --
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cmp_o => alu_cmp, -- comparator status
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cmp_o => alu_cmp, -- comparator status
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add_o => alu_add, -- OPA + OPB
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add_o => alu_add, -- OPA + OPB
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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-- co-processor interface --
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-- co-processor interface --
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cp_opa_o => cp_opa, -- co-processor operand a
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cp_opb_o => cp_opb, -- co-processor operand b
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_start_o => cp1_start, -- trigger co-processor 1
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cp1_data_i => cp1_data, -- co-processor 1 result
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cp1_data_i => cp1_data, -- co-processor 1 result
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| Line 295... |
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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start_i => cp0_start, -- trigger operation
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start_i => cp0_start, -- trigger operation
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rs1_i => cp_opa, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => cp_opb, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
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-- result and status --
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res_o => cp0_data, -- operation result
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res_o => cp0_data, -- operation result
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valid_o => cp0_valid -- data output valid
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valid_o => cp0_valid -- data output valid
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);
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);
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end generate;
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end generate;
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