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-- # * neorv32_cpu_cp_muldiv.vhd : MULDIV co-processor #
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-- # * neorv32_cpu_cp_muldiv.vhd : MULDIV co-processor #
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-- # * neorv32_cpu_ctrl.vhd : CPU control and CSR system #
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-- # * neorv32_cpu_ctrl.vhd : CPU control and CSR system #
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-- # * neorv32_cpu_decompressor.vhd : Compressed instructions decoder #
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-- # * neorv32_cpu_decompressor.vhd : Compressed instructions decoder #
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-- # * neorv32_cpu_regfile.vhd : Data register file #
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-- # * neorv32_cpu_regfile.vhd : Data register file #
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-- # #
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-- # #
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-- # Check the processor's documentary for more information: docs/NEORV32.pdf #
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-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal bus_d_wait : std_ulogic; -- wait for current bus data access
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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-- data input --
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-- data input --
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instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => alu_cmp, -- comparator status
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cmp_i => alu_cmp, -- comparator status
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alu_add_i => alu_add, -- ALU.add result
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alu_res_i => alu_res, -- ALU processing result
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alu_res_i => alu_res, -- ALU processing result
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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pc2_i => curr_pc, -- delayed PC
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pc2_i => curr_pc, -- delayed PC
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imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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-- data output --
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-- data output --
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cmp_o => alu_cmp, -- comparator status
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cmp_o => alu_cmp, -- comparator status
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add_o => alu_add, -- OPA + OPB
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res_o => alu_res, -- ALU result
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res_o => alu_res, -- ALU result
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_start_o => cp0_start, -- trigger co-processor 0
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_data_i => cp0_data, -- co-processor 0 result
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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cp0_valid_i => cp0_valid, -- co-processor 0 result valid
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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--
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--
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ma_instr_o => ma_instr, -- misaligned instruction address
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ma_instr_o => ma_instr, -- misaligned instruction address
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be_instr_o => be_instr, -- bus error on instruction access
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be_instr_o => be_instr, -- bus error on instruction access
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-- cpu data access interface --
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-- cpu data access interface --
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addr_i => alu_add, -- ALU.add result -> access address
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addr_i => alu_res, -- ALU result -> access address
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wdata_i => rs2, -- write data
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wdata_i => rs2, -- write data
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rdata_o => rdata, -- read data
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rdata_o => rdata, -- read data
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mar_o => mar, -- current memory address register
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mar_o => mar, -- current memory address register
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d_wait_o => bus_d_wait, -- wait for access to complete
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d_wait_o => bus_d_wait, -- wait for access to complete
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--
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--
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