| Line 56... |
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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HW_THREAD_ID : std_ulogic_vector(31 downto 0):= (others => '0'); -- hardware thread id
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= (others => '0'); -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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| Line 86... |
Line 87... |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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i_bus_lock_o : out std_ulogic; -- locked/exclusive access
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-- data bus interface --
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-- data bus interface --
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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| Line 98... |
Line 100... |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_lock_o : out std_ulogic; -- locked/exclusive access
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for next to-be-executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data, cp2_data, cp3_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid, cp2_valid, cp3_valid : std_ulogic;
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signal cp0_valid, cp1_valid, cp2_valid, cp3_valid : std_ulogic;
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signal cp0_start, cp1_start, cp2_start, cp3_start : std_ulogic;
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signal cp0_start, cp1_start, cp2_start, cp3_start : std_ulogic;
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| Line 161... |
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assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
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assert not ((PMP_NUM_REGIONS > pmp_max_r_c) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions out of valid range." severity error;
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-- PMP granulartiy --
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-- PMP granulartiy --
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assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < PMP_GRANULARITY < 33)." severity error;
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assert not (((PMP_GRANULARITY < 1) or (PMP_GRANULARITY > 32)) and (PMP_USE = true)) report "NEORV32 CPU CONFIG ERROR! Invalid PMP granulartiy (0 < PMP_GRANULARITY < 33)." severity error;
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-- Instruction prefetch buffer size --
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-- Instruction prefetch buffer size --
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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-- A extension - only lr.w and sc.w supported yet --
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assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports >lr.w< and >sc.w< instructions yet." severity warning;
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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generic map (
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generic map (
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-- General --
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-- General --
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
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HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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| Line 200... |
Line 205... |
rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
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next_pc_o => next_pc, -- next PC (corresponding to current instruction
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i => msw_irq_i, -- machine software interrupt
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msw_irq_i => msw_irq_i, -- machine software interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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| Line 238... |
Line 242... |
ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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mem_i => rdata, -- memory read data
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mem_i => rdata, -- memory read data
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alu_i => alu_res, -- ALU result
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alu_i => alu_res, -- ALU result
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csr_i => csr_rdata, -- CSR read data
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csr_i => csr_rdata, -- CSR read data
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pc_i => next_pc, -- next pc (for linking)
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-- data output --
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-- data output --
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rs1_o => rs1, -- operand 1
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rs1_o => rs1, -- operand 1
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rs2_o => rs2 -- operand 2
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rs2_o => rs2 -- operand 2
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);
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);
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| Line 315... |
Line 318... |
cp0_data <= (others => '0');
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cp0_data <= (others => '0');
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cp0_valid <= '0';
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cp0_valid <= '0';
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end generate;
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end generate;
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-- Co-Processor 1: Not implemented (yet) --------------------------------------------------
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-- Co-Processor 1: Atomic Memory Access (SC - store-conditional) --------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- control: ctrl cp1_start
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atomic_op_cp: process(ctrl, cp1_start)
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-- inputs: rs1 rs2 alu_cmp alu_opb
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begin
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-- "fake" co-processor for atomic operations
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-- used to get the result of a store-conditional operation into the data path
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if (CPU_EXTENSION_RISCV_A = true) and (cp1_start = '1') then
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cp1_data <= (others => '0');
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cp1_data(0) <= not ctrl(ctrl_bus_lock_c);
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cp1_valid <= '1';
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else
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cp1_data <= (others => '0');
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cp1_data <= (others => '0');
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cp1_valid <= '0';
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cp1_valid <= '0';
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end if;
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end process;
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-- Co-Processor 2: Not implemented (yet) --------------------------------------------------
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-- Co-Processor 2: Not implemented (yet) --------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- control: ctrl cp2_start
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-- control: ctrl cp2_start
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| Line 362... |
Line 374... |
i_wait_o => bus_i_wait, -- wait for fetch to complete
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i_wait_o => bus_i_wait, -- wait for fetch to complete
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--
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--
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ma_instr_o => ma_instr, -- misaligned instruction address
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ma_instr_o => ma_instr, -- misaligned instruction address
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be_instr_o => be_instr, -- bus error on instruction access
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be_instr_o => be_instr, -- bus error on instruction access
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-- cpu data access interface --
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-- cpu data access interface --
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addr_i => alu_res, -- ALU result -> access address
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addr_i => alu_add, -- ALU.add result -> access address
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wdata_i => rs2, -- write data
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wdata_i => rs2, -- write data
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rdata_o => rdata, -- read data
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rdata_o => rdata, -- read data
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mar_o => mar, -- current memory address register
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mar_o => mar, -- current memory address register
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d_wait_o => bus_d_wait, -- wait for access to complete
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d_wait_o => bus_d_wait, -- wait for access to complete
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--
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--
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| Line 386... |
Line 398... |
i_bus_re_o => i_bus_re_o, -- read enable
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i_bus_re_o => i_bus_re_o, -- read enable
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i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
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i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
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i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
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i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
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i_bus_err_i => i_bus_err_i, -- bus transfer error
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i_bus_err_i => i_bus_err_i, -- bus transfer error
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i_bus_fence_o => i_bus_fence_o, -- fence operation
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i_bus_fence_o => i_bus_fence_o, -- fence operation
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i_bus_lock_o => i_bus_lock_o, -- locked/exclusive access
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-- data bus --
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-- data bus --
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d_bus_addr_o => d_bus_addr_o, -- bus access address
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d_bus_addr_o => d_bus_addr_o, -- bus access address
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d_bus_rdata_i => d_bus_rdata_i, -- bus read data
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d_bus_rdata_i => d_bus_rdata_i, -- bus read data
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d_bus_wdata_o => d_bus_wdata_o, -- bus write data
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d_bus_wdata_o => d_bus_wdata_o, -- bus write data
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d_bus_ben_o => d_bus_ben_o, -- byte enable
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d_bus_ben_o => d_bus_ben_o, -- byte enable
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d_bus_we_o => d_bus_we_o, -- write enable
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d_bus_we_o => d_bus_we_o, -- write enable
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d_bus_re_o => d_bus_re_o, -- read enable
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d_bus_re_o => d_bus_re_o, -- read enable
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d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
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d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
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d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
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d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
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d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_fence_o => d_bus_fence_o -- fence operation
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d_bus_fence_o => d_bus_fence_o, -- fence operation
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d_bus_lock_o => d_bus_lock_o -- locked/exclusive access
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);
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);
|
|
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-- current privilege level --
|
-- current privilege level --
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i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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