| Line 4... |
Line 4... |
-- # NEORV32 CPU: #
|
-- # NEORV32 CPU: #
|
-- # * neorv32_cpu.vhd - CPU top entity #
|
-- # * neorv32_cpu.vhd - CPU top entity #
|
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
|
-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
|
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
|
-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
|
-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor ('B') #
|
-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor ('B') #
|
-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor ('F') #
|
-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor ('Zfinx') #
|
-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor ('M') #
|
-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor ('M') #
|
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
|
-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
|
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
|
-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
|
-- # * neorv32_cpu_regfile.vhd - Data register file #
|
-- # * neorv32_cpu_regfile.vhd - Data register file #
|
-- # * neorv32_package.vhd - Main CPU/processor package file #
|
-- # * neorv32_package.vhd - Main CPU/processor package file #
|
| Line 62... |
Line 62... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_F : boolean := false; -- implement 32-bit floating-point extension?
|
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
|
| Line 93... |
Line 93... |
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 106... |
Line 105... |
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_fence_o : out std_ulogic; -- executed FENCE operation
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
|
d_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
d_bus_excl_o : out std_ulogic; -- exclusive access request
|
|
d_bus_excl_i : in std_ulogic; -- state of exclusiv access (set if success)
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
|
| Line 130... |
Line 130... |
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu address result
|
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
signal mem_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
|
signal mem_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data
|
|
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
signal alu_wait : std_ulogic; -- alu is busy due to iterative unit
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_i_wait : std_ulogic; -- wait for current bus instruction fetch
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal bus_d_wait : std_ulogic; -- wait for current bus data access
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
|
signal ma_instr : std_ulogic; -- misaligned instruction address
|
signal ma_instr : std_ulogic; -- misaligned instruction address
|
signal ma_load : std_ulogic; -- misaligned load data address
|
signal ma_load : std_ulogic; -- misaligned load data address
|
signal ma_store : std_ulogic; -- misaligned store data address
|
signal ma_store : std_ulogic; -- misaligned store data address
|
|
signal bus_excl_ok : std_ulogic; -- atomic memory access successful
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_instr : std_ulogic; -- bus error on instruction access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_load : std_ulogic; -- bus error on load data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal be_store : std_ulogic; -- bus error on store data access
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
|
signal fpu_mem_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory write-data form FPU
|
|
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
|
signal fpu_rm : std_ulogic_vector(2 downto 0); -- FPU rounding mode
|
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
|
signal fpu_flags : std_ulogic_vector(4 downto 0); -- FPU exception flags
|
|
|
-- co-processor interface --
|
-- co-processor interface --
|
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
|
signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
|
| Line 159... |
Line 158... |
signal pmp_addr : pmp_addr_if_t;
|
signal pmp_addr : pmp_addr_if_t;
|
signal pmp_ctrl : pmp_ctrl_if_t;
|
signal pmp_ctrl : pmp_ctrl_if_t;
|
|
|
-- atomic memory access - success? --
|
-- atomic memory access - success? --
|
signal atomic_sc_res: std_ulogic;
|
signal atomic_sc_res: std_ulogic;
|
|
signal atomic_sc_res_ff : std_ulogic;
|
|
signal atomic_sc_val : std_ulogic;
|
|
|
begin
|
begin
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 182... |
Line 183... |
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
|
assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
|
|
|
-- FIXME: Bit manipulation warning --
|
-- FIXME: Bit manipulation warning --
|
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still HIGHLY EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
|
assert not (CPU_EXTENSION_RISCV_B = true) report "NEORV32 CPU CONFIG WARNING! Bit manipulation extension (B) is still HIGHLY EXPERIMENTAL (and spec. is not ratified yet)." severity warning;
|
|
|
-- FIXME: Floating-point extension warning --
|
-- FIXME: Floating-point extension (Zfinx) warning --
|
assert not (CPU_EXTENSION_RISCV_F = true) report "NEORV32 CPU CONFIG WARNING! 32-bit floating-point extension (F) is WORK-IN-PROGRESS and NOT OPERATIONAL yet." severity warning;
|
assert not (CPU_EXTENSION_RISCV_Zfinx = true) report "NEORV32 CPU CONFIG WARNING! 32-bit floating-point extension (F/Zfinx) is WORK-IN-PROGRESS and NOT OPERATIONAL yet." severity warning;
|
|
|
-- PMP regions check --
|
-- PMP regions check --
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
|
assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
|
-- PMP granulartiy --
|
-- PMP granulartiy --
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
|
assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be a power of two." severity error;
|
assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be >= 8 bytes." severity error;
|
assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! PMP granulartiy has to be >= 8 bytes." severity error;
|
-- PMP notifier --
|
-- PMP notifier --
|
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
|
assert not (PMP_NUM_REGIONS > 0) report "NEORV32 CPU CONFIG NOTE: Implementing physical memory protection (PMP) with " & integer'image(PMP_NUM_REGIONS) & " regions and a minimal granularity of " & integer'image(PMP_MIN_GRANULARITY) & " bytes." severity note;
|
| Line 212... |
Line 213... |
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
CPU_BOOT_ADDR => CPU_BOOT_ADDR, -- cpu boot address
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
|
CPU_EXTENSION_RISCV_F => CPU_EXTENSION_RISCV_F, -- implement 32-bit floating-point extension?
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
| Line 358... |
Line 358... |
-- "pseudo" co-processor for atomic operations
|
-- "pseudo" co-processor for atomic operations
|
-- required to get the result of a store-conditional operation into the data path
|
-- required to get the result of a store-conditional operation into the data path
|
atomic_op_cp: process(clk_i)
|
atomic_op_cp: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (cp_start(1) = '1') then
|
atomic_sc_val <= cp_start(1);
|
atomic_sc_res <= not ctrl(ctrl_bus_lock_c);
|
atomic_sc_res <= bus_excl_ok;
|
|
if (atomic_sc_val = '1') then
|
|
atomic_sc_res_ff <= not atomic_sc_res;
|
else
|
else
|
atomic_sc_res <= '0';
|
atomic_sc_res_ff <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process atomic_op_cp;
|
end process atomic_op_cp;
|
|
|
-- CP result --
|
-- CP result --
|
cp_result(1)(data_width_c-1 downto 1) <= (others => '0');
|
cp_result(1)(data_width_c-1 downto 1) <= (others => '0');
|
cp_result(1)(0) <= atomic_sc_res when (CPU_EXTENSION_RISCV_A = true) else '0';
|
cp_result(1)(0) <= atomic_sc_res_ff when (CPU_EXTENSION_RISCV_A = true) else '0';
|
cp_valid(1) <= cp_start(1); -- always assigned even if A extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(1) <= atomic_sc_val when (CPU_EXTENSION_RISCV_A = true) else cp_start(1); -- assigned even if A extension is disabled so CPU does not get stalled on accidental access
|
|
|
|
|
-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
|
-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_bitmanip_inst_true:
|
neorv32_cpu_cp_bitmanip_inst_true:
|
| Line 408... |
Line 410... |
-- required to get the CSR read data into the data path
|
-- required to get the CSR read data into the data path
|
cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
-- Co-Processor 4: Single-Precision Floating-Point Unit ('F' Extension) -------------------
|
-- Co-Processor 4: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_fpu_inst_true:
|
neorv32_cpu_cp_fpu_inst_true:
|
if (CPU_EXTENSION_RISCV_F = true) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
start_i => cp_start(4), -- trigger operation
|
start_i => cp_start(4), -- trigger operation
|
-- data input --
|
-- data input --
|
frm_i => fpu_rm, -- rounding mode
|
frm_i => fpu_rm, -- rounding mode
|
reg_i => rs1, -- rf source
|
rs1_i => rs1, -- rf source 1
|
mem_i => mem_rdata, -- memory read-data
|
rs2_i => rs2, -- rf source 2
|
-- result and status --
|
-- result and status --
|
fflags_o => fpu_flags, -- exception flags
|
|
mem_o => fpu_mem_wdata, -- memory write-data
|
|
res_o => cp_result(4), -- operation result
|
res_o => cp_result(4), -- operation result
|
|
fflags_o => fpu_flags, -- exception flags
|
valid_o => cp_valid(4) -- data output valid
|
valid_o => cp_valid(4) -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
neorv32_cpu_cp_fpu_inst_false:
|
if (CPU_EXTENSION_RISCV_F = false) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
fpu_flags <= (others => '0');
|
|
fpu_mem_wdata <= (others => '0');
|
|
cp_result(4) <= (others => '0');
|
cp_result(4) <= (others => '0');
|
|
fpu_flags <= (others => '0');
|
cp_valid(4) <= cp_start(4); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(4) <= cp_start(4); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 5..7: Not Implemented Yet -------------------------------------------------
|
-- Co-Processor 5..7: Not Implemented Yet -------------------------------------------------
|
| Line 456... |
Line 456... |
|
|
-- Bus Interface Unit ---------------------------------------------------------------------
|
-- Bus Interface Unit ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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neorv32_cpu_bus_inst: neorv32_cpu_bus
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generic map (
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generic map (
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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-- Physical memory protection (PMP) --
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-- Physical memory protection (PMP) --
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Bus Timeout --
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-- Bus Timeout --
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| Line 477... |
Line 478... |
--
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--
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ma_instr_o => ma_instr, -- misaligned instruction address
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ma_instr_o => ma_instr, -- misaligned instruction address
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be_instr_o => be_instr, -- bus error on instruction access
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be_instr_o => be_instr, -- bus error on instruction access
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-- cpu data access interface --
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-- cpu data access interface --
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addr_i => alu_add, -- ALU.add result -> access address
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addr_i => alu_add, -- ALU.add result -> access address
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wdata_i => mem_wdata, -- write data
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wdata_i => rs2, -- write data
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rdata_o => mem_rdata, -- read data
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rdata_o => mem_rdata, -- read data
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mar_o => mar, -- current memory address register
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mar_o => mar, -- current memory address register
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d_wait_o => bus_d_wait, -- wait for access to complete
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d_wait_o => bus_d_wait, -- wait for access to complete
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--
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--
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bus_excl_ok_o => bus_excl_ok, -- bus exclusive access successful
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ma_load_o => ma_load, -- misaligned load data address
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ma_load_o => ma_load, -- misaligned load data address
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ma_store_o => ma_store, -- misaligned store data address
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ma_store_o => ma_store, -- misaligned store data address
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be_load_o => be_load, -- bus error on load data access
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be_load_o => be_load, -- bus error on load data access
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be_store_o => be_store, -- bus error on store data access
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be_store_o => be_store, -- bus error on store data access
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-- physical memory protection --
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-- physical memory protection --
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| Line 500... |
Line 502... |
i_bus_re_o => i_bus_re_o, -- read enable
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i_bus_re_o => i_bus_re_o, -- read enable
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i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
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i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
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i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
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i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
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i_bus_err_i => i_bus_err_i, -- bus transfer error
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i_bus_err_i => i_bus_err_i, -- bus transfer error
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i_bus_fence_o => i_bus_fence_o, -- fence operation
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i_bus_fence_o => i_bus_fence_o, -- fence operation
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i_bus_lock_o => i_bus_lock_o, -- locked/exclusive access
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-- data bus --
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-- data bus --
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d_bus_addr_o => d_bus_addr_o, -- bus access address
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d_bus_addr_o => d_bus_addr_o, -- bus access address
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d_bus_rdata_i => d_bus_rdata_i, -- bus read data
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d_bus_rdata_i => d_bus_rdata_i, -- bus read data
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d_bus_wdata_o => d_bus_wdata_o, -- bus write data
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d_bus_wdata_o => d_bus_wdata_o, -- bus write data
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d_bus_ben_o => d_bus_ben_o, -- byte enable
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d_bus_ben_o => d_bus_ben_o, -- byte enable
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| Line 512... |
Line 513... |
d_bus_re_o => d_bus_re_o, -- read enable
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d_bus_re_o => d_bus_re_o, -- read enable
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d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
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d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
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d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
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d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
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d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_err_i => d_bus_err_i, -- bus transfer error
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d_bus_fence_o => d_bus_fence_o, -- fence operation
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d_bus_fence_o => d_bus_fence_o, -- fence operation
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d_bus_lock_o => d_bus_lock_o -- locked/exclusive access
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d_bus_excl_o => d_bus_excl_o, -- exclusive access request
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d_bus_excl_i => d_bus_excl_i -- state of exclusiv access (set if success)
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);
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);
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-- memory write data --
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mem_wdata <= fpu_mem_wdata when ((CPU_EXTENSION_RISCV_F = true) and (ctrl(ctrl_bus_wd_sel_c) = '1')) else rs2;
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-- current privilege level --
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-- current privilege level --
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i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
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