| Line 56... |
Line 56... |
entity neorv32_cpu is
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entity neorv32_cpu is
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generic (
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generic (
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-- General --
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-- General --
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit)
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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CPU_BOOT_ADDR : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
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BUS_TIMEOUT : natural := 63; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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| Line 91... |
Line 90... |
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_we_o : out std_ulogic; -- write enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_re_o : out std_ulogic; -- read enable
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i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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i_bus_lock_o : out std_ulogic; -- exclusive access request
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_fence_o : out std_ulogic; -- executed FENCEI operation
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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i_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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-- data bus interface --
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-- data bus interface --
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| Line 103... |
Line 102... |
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_we_o : out std_ulogic; -- write enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_re_o : out std_ulogic; -- read enable
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d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
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d_bus_lock_o : out std_ulogic; -- exclusive access request
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_ack_i : in std_ulogic := '0'; -- bus transfer acknowledge
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_err_i : in std_ulogic := '0'; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_excl_o : out std_ulogic; -- exclusive access request
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d_bus_excl_i : in std_ulogic; -- state of exclusiv access (set if success)
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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time_i : in std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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mext_irq_i : in std_ulogic := '0'; -- machine external interrupt
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| Line 141... |
Line 138... |
signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal csr_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- csr read data
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal mar : std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_instr : std_ulogic; -- misaligned instruction address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_load : std_ulogic; -- misaligned load data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal bus_excl_ok : std_ulogic; -- atomic memory access successful
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signal excl_state : std_ulogic; -- atomic/exclusive access lock status
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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| Line 159... |
Line 156... |
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-- pmp interface --
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-- pmp interface --
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_addr : pmp_addr_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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signal pmp_ctrl : pmp_ctrl_if_t;
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-- atomic memory access - success? --
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signal atomic_sc_res : std_ulogic;
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signal atomic_sc_res_ff : std_ulogic;
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signal atomic_sc_val : std_ulogic;
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begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- hardware reset notifier --
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-- hardware reset notifier --
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| Line 183... |
Line 175... |
assert not (CPU_CNT_WIDTH < 64) report "NEORV32 CPU CONFIG WARNING! Implementing CPU <cycle> and <instret> CSRs with reduced size (" & integer'image(CPU_CNT_WIDTH) & "-bit instead of 64-bit). This is not RISC-V compliant and might have unintended SW side effects." severity warning;
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assert not (CPU_CNT_WIDTH < 64) report "NEORV32 CPU CONFIG WARNING! Implementing CPU <cycle> and <instret> CSRs with reduced size (" & integer'image(CPU_CNT_WIDTH) & "-bit instead of 64-bit). This is not RISC-V compliant and might have unintended SW side effects." severity warning;
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|
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-- U-extension requires Zicsr extension --
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-- U-extension requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (CPU_EXTENSION_RISCV_U = true)) report "NEORV32 CPU CONFIG ERROR! User mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Bus timeout --
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assert not (BUS_TIMEOUT < 2) report "NEORV32 CPU CONFIG ERROR! Invalid bus access timeout value <BUS_TIMEOUT>. Has to be >= 2." severity error;
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-- Instruction prefetch buffer size --
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-- Instruction prefetch buffer size --
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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assert not (is_power_of_two_f(ipb_entries_c) = false) report "NEORV32 CPU CONFIG ERROR! Number of entries in instruction prefetch buffer <ipb_entries_c> has to be a power of two." severity error;
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-- A extension - only lr.w and sc.w are supported yet --
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-- A extension - only lr.w and sc.w are supported yet --
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assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
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assert not (CPU_EXTENSION_RISCV_A = true) report "NEORV32 CPU CONFIG WARNING! Atomic operations extension (A) only supports <lr.w> and <sc.w> instructions." severity warning;
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| Line 250... |
Line 239... |
ctrl_o => ctrl, -- main control bus
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ctrl_o => ctrl, -- main control bus
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-- status input --
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-- status input --
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alu_wait_i => alu_wait, -- wait for ALU
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alu_wait_i => alu_wait, -- wait for ALU
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_i_wait_i => bus_i_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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bus_d_wait_i => bus_d_wait, -- wait for bus
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excl_state_i => excl_state, -- atomic/exclusive access lock status
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-- data input --
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-- data input --
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instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => comparator, -- comparator status
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cmp_i => comparator, -- comparator status
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alu_add_i => alu_add, -- ALU address result
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alu_add_i => alu_add, -- ALU address result
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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| Line 339... |
Line 329... |
-- status --
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-- status --
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wait_o => alu_wait -- busy due to iterative processing units
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wait_o => alu_wait -- busy due to iterative processing units
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);
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);
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-- Co-Processor 0: Integer Multiplication/Division ('M' Extension) ------------------------
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-- Co-Processor 0: CSR (Read) Access ('Zicsr' Extension) ----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- "pseudo" co-processor for CSR *read* access operations
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-- required to get CSR read data into the data path
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cp_result(0) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
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cp_valid(0) <= cp_start(0); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
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|
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-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_muldiv_inst_true:
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neorv32_cpu_cp_muldiv_inst_true:
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if (CPU_EXTENSION_RISCV_M = true) generate
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if (CPU_EXTENSION_RISCV_M = true) generate
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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generic map (
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generic map (
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| Line 352... |
Line 350... |
port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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start_i => cp_start(0), -- trigger operation
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start_i => cp_start(1), -- trigger operation
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-- data input --
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-- data input --
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rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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-- result and status --
|
-- result and status --
|
res_o => cp_result(0), -- operation result
|
res_o => cp_result(1), -- operation result
|
valid_o => cp_valid(0) -- data output valid
|
valid_o => cp_valid(1) -- data output valid
|
);
|
);
|
end generate;
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end generate;
|
|
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neorv32_cpu_cp_muldiv_inst_false:
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neorv32_cpu_cp_muldiv_inst_false:
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if (CPU_EXTENSION_RISCV_M = false) generate
|
if (CPU_EXTENSION_RISCV_M = false) generate
|
cp_result(0) <= (others => '0');
|
cp_result(1) <= (others => '0');
|
cp_valid(0) <= cp_start(0); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
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end generate;
|
|
|
|
|
-- Co-Processor 1: Atomic Memory Access ('A' Extension) -----------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
-- "pseudo" co-processor for atomic operations
|
|
-- required to get the result of a store-conditional operation into the data path
|
|
atomic_op_cp: process(rstn_i, clk_i)
|
|
begin
|
|
if (rstn_i = '0') then
|
|
atomic_sc_val <= def_rst_val_c;
|
|
atomic_sc_res <= def_rst_val_c;
|
|
atomic_sc_res_ff <= def_rst_val_c;
|
|
elsif rising_edge(clk_i) then
|
|
atomic_sc_val <= cp_start(1);
|
|
atomic_sc_res <= bus_excl_ok;
|
|
if (atomic_sc_val = '1') then
|
|
atomic_sc_res_ff <= not atomic_sc_res;
|
|
else
|
|
atomic_sc_res_ff <= '0';
|
|
end if;
|
|
end if;
|
|
end process atomic_op_cp;
|
|
|
|
-- CP result --
|
|
cp_result(1)(data_width_c-1 downto 1) <= (others => '0');
|
|
cp_result(1)(0) <= atomic_sc_res_ff when (CPU_EXTENSION_RISCV_A = true) else '0';
|
|
cp_valid(1) <= atomic_sc_val when (CPU_EXTENSION_RISCV_A = true) else cp_start(1); -- assigned even if A extension is disabled so CPU does not get stalled on accidental access
|
|
|
|
|
|
-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
|
-- Co-Processor 2: Bit Manipulation ('B' Extension) ---------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_bitmanip_inst_true:
|
neorv32_cpu_cp_bitmanip_inst_true:
|
if (CPU_EXTENSION_RISCV_B = true) generate
|
if (CPU_EXTENSION_RISCV_B = true) generate
|
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
|
neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
|
| Line 424... |
Line 395... |
cp_result(2) <= (others => '0');
|
cp_result(2) <= (others => '0');
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 3: CSR (Read) Access ('Zicsr' Extension) ----------------------------------
|
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
-- -------------------------------------------------------------------------------------------
|
|
-- "pseudo" co-processor for CSR *read* access operations
|
|
-- required to get CSR read data into the data path
|
|
cp_result(3) <= csr_rdata when (CPU_EXTENSION_RISCV_Zicsr = true) else (others => '0');
|
|
cp_valid(3) <= cp_start(3); -- always assigned even if Zicsr extension is disabled to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
|
-- Co-Processor 4: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_cp_fpu_inst_true:
|
neorv32_cpu_cp_fpu_inst_true:
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
start_i => cp_start(4), -- trigger operation
|
start_i => cp_start(3), -- trigger operation
|
-- data input --
|
-- data input --
|
frm_i => fpu_rm, -- rounding mode
|
frm_i => fpu_rm, -- rounding mode
|
cmp_i => comparator, -- comparator status
|
cmp_i => comparator, -- comparator status
|
rs1_i => rs1, -- rf source 1
|
rs1_i => rs1, -- rf source 1
|
rs2_i => rs2, -- rf source 2
|
rs2_i => rs2, -- rf source 2
|
-- result and status --
|
-- result and status --
|
res_o => cp_result(4), -- operation result
|
res_o => cp_result(3), -- operation result
|
fflags_o => fpu_flags, -- exception flags
|
fflags_o => fpu_flags, -- exception flags
|
valid_o => cp_valid(4) -- data output valid
|
valid_o => cp_valid(3) -- data output valid
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
neorv32_cpu_cp_fpu_inst_false:
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
cp_result(4) <= (others => '0');
|
cp_result(3) <= (others => '0');
|
fpu_flags <= (others => '0');
|
fpu_flags <= (others => '0');
|
cp_valid(4) <= cp_start(4); -- to make sure CPU does not get stalled if there is an accidental access
|
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
|
end generate;
|
end generate;
|
|
|
|
|
-- Co-Processor 5,6,7: Not Implemented Yet ------------------------------------------------
|
-- Co-Processor 4,5,6,7: Not Implemented --------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
cp_result(4) <= (others => '0');
|
|
cp_valid(4) <= '0';
|
|
--
|
cp_result(5) <= (others => '0');
|
cp_result(5) <= (others => '0');
|
cp_valid(5) <= '0';
|
cp_valid(5) <= '0';
|
--
|
--
|
cp_result(6) <= (others => '0');
|
cp_result(6) <= (others => '0');
|
cp_valid(6) <= '0';
|
cp_valid(6) <= '0';
|
| Line 483... |
Line 449... |
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
-- Physical memory protection (PMP) --
|
-- Physical memory protection (PMP) --
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..64)
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
|
-- Bus Timeout --
|
|
BUS_TIMEOUT => BUS_TIMEOUT -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
|
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
| Line 506... |
Line 470... |
wdata_i => rs2, -- write data
|
wdata_i => rs2, -- write data
|
rdata_o => mem_rdata, -- read data
|
rdata_o => mem_rdata, -- read data
|
mar_o => mar, -- current memory address register
|
mar_o => mar, -- current memory address register
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
d_wait_o => bus_d_wait, -- wait for access to complete
|
--
|
--
|
bus_excl_ok_o => bus_excl_ok, -- bus exclusive access successful
|
excl_state_o => excl_state, -- atomic/exclusive access status
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_load_o => ma_load, -- misaligned load data address
|
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
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be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
-- physical memory protection --
|
-- physical memory protection --
|
| Line 521... |
Line 485... |
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_rdata_i => i_bus_rdata_i, -- bus read data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_wdata_o => i_bus_wdata_o, -- bus write data
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
i_bus_ben_o => i_bus_ben_o, -- byte enable
|
i_bus_we_o => i_bus_we_o, -- write enable
|
i_bus_we_o => i_bus_we_o, -- write enable
|
i_bus_re_o => i_bus_re_o, -- read enable
|
i_bus_re_o => i_bus_re_o, -- read enable
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i_bus_cancel_o => i_bus_cancel_o, -- cancel current bus transaction
|
i_bus_lock_o => i_bus_lock_o, -- exclusive access request
|
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
|
i_bus_ack_i => i_bus_ack_i, -- bus transfer acknowledge
|
i_bus_err_i => i_bus_err_i, -- bus transfer error
|
i_bus_err_i => i_bus_err_i, -- bus transfer error
|
i_bus_fence_o => i_bus_fence_o, -- fence operation
|
i_bus_fence_o => i_bus_fence_o, -- fence operation
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o => d_bus_addr_o, -- bus access address
|
d_bus_addr_o => d_bus_addr_o, -- bus access address
|
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
|
d_bus_rdata_i => d_bus_rdata_i, -- bus read data
|
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
|
d_bus_wdata_o => d_bus_wdata_o, -- bus write data
|
d_bus_ben_o => d_bus_ben_o, -- byte enable
|
d_bus_ben_o => d_bus_ben_o, -- byte enable
|
d_bus_we_o => d_bus_we_o, -- write enable
|
d_bus_we_o => d_bus_we_o, -- write enable
|
d_bus_re_o => d_bus_re_o, -- read enable
|
d_bus_re_o => d_bus_re_o, -- read enable
|
d_bus_cancel_o => d_bus_cancel_o, -- cancel current bus transaction
|
d_bus_lock_o => d_bus_lock_o, -- exclusive access request
|
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
|
d_bus_ack_i => d_bus_ack_i, -- bus transfer acknowledge
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
d_bus_err_i => d_bus_err_i, -- bus transfer error
|
d_bus_fence_o => d_bus_fence_o, -- fence operation
|
d_bus_fence_o => d_bus_fence_o -- fence operation
|
d_bus_excl_o => d_bus_excl_o, -- exclusive access request
|
|
d_bus_excl_i => d_bus_excl_i -- state of exclusiv access (set if success)
|
|
);
|
);
|
|
|
-- current privilege level --
|
-- current privilege level --
|
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
i_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
d_bus_priv_o <= ctrl(ctrl_priv_lvl_msb_c downto ctrl_priv_lvl_lsb_c);
|
