| Line 51... |
Line 51... |
generic (
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generic (
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-- General --
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-- General --
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
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CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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| Line 107... |
Line 108... |
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-- local signals --
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-- local signals --
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal alu_cmp : std_ulogic_vector(1 downto 0); -- alu comparator result
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal imm : std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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signal pc : std_ulogic_vector(data_width_c-1 downto 0); -- current program counter
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signal pc_delayed : std_ulogic_vector(data_width_c-1 downto 0); -- delayed program counter
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal instr : std_ulogic_vector(data_width_c-1 downto 0); -- new instruction
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal rs1, rs2 : std_ulogic_vector(data_width_c-1 downto 0); -- source registers
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal alu_add : std_ulogic_vector(data_width_c-1 downto 0); -- alu adder result
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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signal rdata : std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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| Line 125... |
Line 124... |
signal ma_store : std_ulogic; -- misaligned store data address
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signal ma_store : std_ulogic; -- misaligned store data address
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_instr : std_ulogic; -- bus error on instruction access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_load : std_ulogic; -- bus error on load data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal be_store : std_ulogic; -- bus error on store data access
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signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
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signal bus_exc_ack : std_ulogic; -- bus exception error acknowledge
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signal bus_busy : std_ulogic; -- bus unit is busy
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signal fetch_pc : std_ulogic_vector(data_width_c-1 downto 0); -- pc for instruction fetch
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signal curr_pc : std_ulogic_vector(data_width_c-1 downto 0); -- current pc (for current executed instruction)
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signal next_pc : std_ulogic_vector(data_width_c-1 downto 0); -- next pc (for current executed instruction)
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-- co-processor interface --
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-- co-processor interface --
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_data, cp1_data : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp0_valid, cp1_valid : std_ulogic;
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signal cp0_valid, cp1_valid : std_ulogic;
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|
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| Line 140... |
Line 143... |
generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz
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HART_ID => HART_ID, -- custom hardware thread ID
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HART_ID => HART_ID, -- custom hardware thread ID
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
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BOOTLOADER_USE => BOOTLOADER_USE, -- implement processor-internal bootloader?
|
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CSR_COUNTERS_USE => CSR_COUNTERS_USE, -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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| Line 184... |
Line 188... |
instr_i => instr, -- instruction
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instr_i => instr, -- instruction
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cmp_i => alu_cmp, -- comparator status
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cmp_i => alu_cmp, -- comparator status
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alu_add_i => alu_add, -- ALU.add result
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alu_add_i => alu_add, -- ALU.add result
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-- data output --
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-- data output --
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imm_o => imm, -- immediate
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imm_o => imm, -- immediate
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pc_o => pc, -- current PC
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fetch_pc_o => fetch_pc, -- PC for instruction fetch
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alu_pc_o => pc_delayed, -- delayed PC for ALU
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curr_pc_o => curr_pc, -- current PC (corresponding to current instruction)
|
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next_pc_o => next_pc, -- next PC (corresponding to current instruction)
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-- csr interface --
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-- csr interface --
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csr_wdata_i => alu_res, -- CSR write data
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csr_wdata_i => alu_res, -- CSR write data
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csr_rdata_o => csr_rdata, -- CSR read data
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csr_rdata_o => csr_rdata, -- CSR read data
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-- external interrupt --
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-- external interrupt --
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clic_irq_i => clic_irq_i, -- CLIC interrupt request
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clic_irq_i => clic_irq_i, -- CLIC interrupt request
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| Line 200... |
Line 205... |
ma_load_i => ma_load, -- misaligned load data address
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ma_load_i => ma_load, -- misaligned load data address
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ma_store_i => ma_store, -- misaligned store data address
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ma_store_i => ma_store, -- misaligned store data address
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be_instr_i => be_instr, -- bus error on instruction access
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be_instr_i => be_instr, -- bus error on instruction access
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be_load_i => be_load, -- bus error on load data access
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be_load_i => be_load, -- bus error on load data access
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be_store_i => be_store, -- bus error on store data access
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be_store_i => be_store, -- bus error on store data access
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bus_exc_ack_o => bus_exc_ack -- bus exception error acknowledge
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bus_exc_ack_o => bus_exc_ack, -- bus exception error acknowledge
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bus_busy_i => bus_busy -- bus unit is busy
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);
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);
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|
|
|
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-- Register File --------------------------------------------------------------------------
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-- Register File --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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| Line 218... |
Line 224... |
ctrl_i => ctrl, -- main control bus
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ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
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mem_i => rdata, -- memory read data
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mem_i => rdata, -- memory read data
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alu_i => alu_res, -- ALU result
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alu_i => alu_res, -- ALU result
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csr_i => csr_rdata, -- CSR read data
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csr_i => csr_rdata, -- CSR read data
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pc_i => pc, -- current pc
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pc_i => next_pc, -- next pc
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-- data output --
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-- data output --
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rs1_o => rs1, -- operand 1
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rs1_o => rs1, -- operand 1
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rs2_o => rs2 -- operand 2
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rs2_o => rs2 -- operand 2
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);
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);
|
|
|
|
|
-- ALU ------------------------------------------------------------------------------------
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-- ALU ------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_alu_inst: neorv32_cpu_alu
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neorv32_cpu_alu_inst: neorv32_cpu_alu
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generic map (
|
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M -- implement mul/div extension?
|
|
)
|
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
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-- data input --
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-- data input --
|
rs1_i => rs1, -- rf source 1
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rs1_i => rs1, -- rf source 1
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rs2_i => rs2, -- rf source 2
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rs2_i => rs2, -- rf source 2
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pc_i => pc, -- current PC
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pc2_i => curr_pc, -- delayed PC
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pc2_i => pc_delayed, -- delayed PC
|
|
imm_i => imm, -- immediate
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imm_i => imm, -- immediate
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csr_i => csr_rdata, -- csr read data
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csr_i => csr_rdata, -- csr read data
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-- data output --
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-- data output --
|
cmp_o => alu_cmp, -- comparator status
|
cmp_o => alu_cmp, -- comparator status
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add_o => alu_add, -- OPA + OPB
|
add_o => alu_add, -- OPA + OPB
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| Line 294... |
Line 295... |
|
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-- Bus Unit -------------------------------------------------------------------------------
|
-- Bus Unit -------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
neorv32_cpu_bus_inst: neorv32_cpu_bus
|
generic map (
|
generic map (
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
)
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)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => rstn_i, -- global reset, low-active, async
|
rstn_i => rstn_i, -- global reset, low-active, async
|
ctrl_i => ctrl, -- main control bus
|
ctrl_i => ctrl, -- main control bus
|
-- data input --
|
-- data input --
|
wdata_i => rs2, -- write data
|
wdata_i => rs2, -- write data
|
pc_i => pc, -- current PC
|
pc_i => fetch_pc, -- current PC for instruction fetch
|
alu_i => alu_res, -- ALU result
|
alu_i => alu_res, -- ALU result
|
-- data output --
|
-- data output --
|
instr_o => instr, -- instruction
|
instr_o => instr, -- instruction
|
rdata_o => rdata, -- read data
|
rdata_o => rdata, -- read data
|
-- status --
|
-- status --
|
| Line 318... |
Line 318... |
ma_store_o => ma_store, -- misaligned store data address
|
ma_store_o => ma_store, -- misaligned store data address
|
be_instr_o => be_instr, -- bus error on instruction access
|
be_instr_o => be_instr, -- bus error on instruction access
|
be_load_o => be_load, -- bus error on load data access
|
be_load_o => be_load, -- bus error on load data access
|
be_store_o => be_store, -- bus error on store data access
|
be_store_o => be_store, -- bus error on store data access
|
bus_wait_o => bus_wait, -- wait for bus operation to finish
|
bus_wait_o => bus_wait, -- wait for bus operation to finish
|
|
bus_busy_o => bus_busy, -- bus unit is busy
|
exc_ack_i => bus_exc_ack, -- exception controller ACK
|
exc_ack_i => bus_exc_ack, -- exception controller ACK
|
-- bus system --
|
-- bus system --
|
bus_addr_o => bus_addr_o, -- bus access address
|
bus_addr_o => bus_addr_o, -- bus access address
|
bus_rdata_i => bus_rdata_i, -- bus read data
|
bus_rdata_i => bus_rdata_i, -- bus read data
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
bus_wdata_o => bus_wdata_o, -- bus write data
|
