| Line 2... |
Line 2... |
-- # << NEORV32 - CPU Top Entity >> #
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-- # << NEORV32 - CPU Top Entity >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # NEORV32 CPU: #
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-- # NEORV32 CPU: #
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-- # * neorv32_cpu.vhd - CPU top entity #
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-- # * neorv32_cpu.vhd - CPU top entity #
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-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
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-- # * neorv32_cpu_alu.vhd - Arithmetic/logic unit #
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-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor #
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-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor #
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-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor #
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-- # * neorv32_cpu_cp_shifter.vhd - Base ISA shifter unit #
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-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
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-- # * neorv32_cpu_bus.vhd - Instruction and data bus interface unit #
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-- # * neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor ('B') #
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-- # * neorv32_cpu_control.vhd - CPU control and CSR system #
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-- # * neorv32_cpu_cp_fpu.vhd - Single-precision FPU co-processor ('Zfinx') #
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-- # * neorv32_cpu_cp_muldiv.vhd - Integer multiplier/divider co-processor ('M') #
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-- # * neorv32_cpu_ctrl.vhd - CPU control and CSR system #
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-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
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-- # * neorv32_cpu_decompressor.vhd - Compressed instructions decoder #
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-- # * neorv32_cpu_regfile.vhd - Data register file #
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-- # * neorv32_cpu_regfile.vhd - Data register file #
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-- # * neorv32_package.vhd - Main CPU & Processor package file #
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-- # * neorv32_package.vhd - Main CPU & Processor package file #
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-- # #
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-- # #
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-- # Check out the processor's data sheet for more information: docs/NEORV32.pdf #
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-- # Check out the CPU's online documentation for more information: #
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-- # HQ: https://github.com/stnolting/neorv32 #
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-- # Data Sheet: https://stnolting.github.io/neorv32 #
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-- # User Guide: https://stnolting.github.io/neorv32/ug #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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Line 67... |
CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
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CPU_EXTENSION_RISCV_A : boolean; -- implement atomic extension?
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CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
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CPU_EXTENSION_RISCV_U : boolean; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG : boolean; -- implement CPU debug mode?
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Line 171... |
cond_sel_string_f(CPU_EXTENSION_RISCV_E, "RV32E", "RV32I") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_E, "RV32E", "RV32I") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_M, "M", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_A, "A", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_C, "C", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_U, "U", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zbb, "_Zbb", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zicsr, "_Zicsr", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zifencei, "_Zifencei", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zfinx, "_Zfinx", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_Zmmul, "_Zmmul", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_Debug", "") &
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cond_sel_string_f(CPU_EXTENSION_RISCV_DEBUG, "_Debug", "") &
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| Line 199... |
Line 205... |
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-- Co-processor timeout counter (for debugging only) --
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-- Co-processor timeout counter (for debugging only) --
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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assert not (cp_timeout_en_c = true) report "NEORV32 CPU CONFIG WARNING! Co-processor timeout counter enabled. This should be used for debugging/simulation only." severity warning;
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-- PMP regions check --
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-- PMP regions check --
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assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out xf valid range (0..64)." severity error;
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assert not (PMP_NUM_REGIONS > 64) report "NEORV32 CPU CONFIG ERROR! Number of PMP regions <PMP_NUM_REGIONS> out of valid range (0..64)." severity error;
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-- PMP granularity --
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-- PMP granularity --
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assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
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assert not ((is_power_of_two_f(PMP_MIN_GRANULARITY) = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be a power of two." severity error;
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assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
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assert not ((PMP_MIN_GRANULARITY < 8) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! <PMP_MIN_GRANULARITY> has to be >= 8 bytes." severity error;
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-- PMP requires Zicsr extension --
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-- PMP requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (PMP_NUM_REGIONS > 0)) report "NEORV32 CPU CONFIG ERROR! Physical memory protection (PMP) requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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Line 219... |
assert not ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
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assert not ((HPM_CNT_WIDTH < 0) or (HPM_CNT_WIDTH > 64)) report "NEORV32 CPU CONFIG ERROR! HPM counter width <HPM_CNT_WIDTH> has to be 0..64 bit." severity error;
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-- HPM CNT requires Zicsr extension --
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-- HPM CNT requires Zicsr extension --
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_Zicsr = false) and (HPM_NUM_CNTS > 0)) report "NEORV32 CPU CONFIG ERROR! Hardware performance monitors (HPM) require <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- Mul-extension --
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-- Mul-extension --
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <ZMMUL> extensions cannot co-exist!" severity error;
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
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-- Debug mode --
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-- Debug mode --
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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-- fast multiplication option --
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assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_MUL_EN> set. Trying to use DSP blocks for base ISA multiplications." severity note;
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-- fast shift option --
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assert not (FAST_SHIFT_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_SHIFT_EN> set. Implementing full-parallel logic / barrel shifters." severity note;
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-- Control Unit ---------------------------------------------------------------------------
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-- Control Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_control_inst: neorv32_cpu_control
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neorv32_cpu_control_inst: neorv32_cpu_control
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generic map (
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generic map (
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| Line 233... |
Line 245... |
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zbb => CPU_EXTENSION_RISCV_Zbb, -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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CPU_EXTENSION_RISCV_DEBUG => CPU_EXTENSION_RISCV_DEBUG, -- implement CPU debug mode?
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| Line 325... |
Line 338... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_alu_inst: neorv32_cpu_alu
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neorv32_cpu_alu_inst: neorv32_cpu_alu
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generic map (
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generic map (
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension?
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CPU_EXTENSION_RISCV_Zbb => CPU_EXTENSION_RISCV_Zbb, -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!)
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
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FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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