| Line 116... |
Line 116... |
d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_err_i : in std_ulogic; -- bus transfer error
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_fence_o : out std_ulogic; -- executed FENCE operation
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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d_bus_priv_o : out std_ulogic_vector(1 downto 0); -- privilege level
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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time_i : in std_ulogic_vector(63 downto 0); -- current system time
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-- non-maskable interrupt --
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nm_irq_i : in std_ulogic; -- NMI
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i : in std_ulogic;-- machine software interrupt
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msw_irq_i : in std_ulogic;-- machine software interrupt
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mext_irq_i : in std_ulogic;-- machine external interrupt
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mext_irq_i : in std_ulogic;-- machine external interrupt
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mtime_irq_i : in std_ulogic;-- machine timer interrupt
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mtime_irq_i : in std_ulogic;-- machine timer interrupt
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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| Line 223... |
Line 221... |
-- Mul-extension --
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-- Mul-extension --
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
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assert not ((CPU_EXTENSION_RISCV_Zmmul = true) and (CPU_EXTENSION_RISCV_M = true)) report "NEORV32 CPU CONFIG ERROR! <M> and <Zmmul> extensions cannot co-exist!" severity error;
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-- Debug mode --
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-- Debug mode --
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zicsr = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zicsr> extension to be enabled." severity error;
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assert not ((CPU_EXTENSION_RISCV_DEBUG = true) and (CPU_EXTENSION_RISCV_Zifencei = false)) report "NEORV32 CPU CONFIG ERROR! Debug mode requires <CPU_EXTENSION_RISCV_Zifencei> extension to be enabled." severity error;
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-- fast multiplication option --
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-- fast multiplication option --
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assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_MUL_EN> set. Trying to use DSP blocks for base ISA multiplications." severity note;
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assert not (FAST_MUL_EN = true) report "NEORV32 CPU CONFIG NOTE: <FAST_MUL_EN> set. Trying to use DSP blocks for base ISA multiplications." severity note;
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-- fast shift option --
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-- fast shift option --
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| Line 289... |
Line 288... |
db_halt_req_i => db_halt_req_i,
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db_halt_req_i => db_halt_req_i,
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-- interrupts (risc-v compliant) --
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-- interrupts (risc-v compliant) --
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msw_irq_i => msw_irq_i, -- machine software interrupt
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msw_irq_i => msw_irq_i, -- machine software interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mext_irq_i => mext_irq_i, -- machine external interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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mtime_irq_i => mtime_irq_i, -- machine timer interrupt
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-- non-maskable interrupt --
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nm_irq_i => nm_irq_i, -- nmi
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-- fast interrupts (custom) --
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-- fast interrupts (custom) --
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firq_i => firq_i, -- fast interrupt trigger
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firq_i => firq_i, -- fast interrupt trigger
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-- system time input from MTIME --
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-- system time input from MTIME --
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time_i => time_i, -- current system time
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time_i => time_i, -- current system time
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-- physical memory protection --
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-- physical memory protection --
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