| Line 111... |
Line 111... |
rb_ff0 : std_ulogic;
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rb_ff0 : std_ulogic;
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rb_ff1 : std_ulogic;
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rb_ff1 : std_ulogic;
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end record;
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end record;
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signal cp_ctrl : cp_ctrl_t;
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signal cp_ctrl : cp_ctrl_t;
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-- bit manipulation --
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signal bitm_res : std_ulogic_vector(31 downto 0);
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
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input_op_mux: process(ctrl_i, csr_i, pc2_i, rs1_i, rs2_i, imm_i)
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| Line 161... |
Line 164... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
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add_res <= std_ulogic_vector(unsigned(opa) + unsigned(opb));
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add_o <= add_res; -- direct output
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add_o <= add_res; -- direct output
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-- Bit Manipulation Unit ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- ------------------ --
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-- UNDER CONSTRUCTION --
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-- ------------------ --
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--bitm_minmax <= rs1_i when ((cmp_less xor ???) = '1') else rs2_i; -- min[u] / max[u]
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-- result of bit manipulation operation --
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bitm_res <= opa and (not opb); -- ANDN
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-- Iterative Shifter Unit -----------------------------------------------------------------
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-- Iterative Shifter Unit -----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(rstn_i, clk_i)
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shifter_unit: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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| Line 175... |
Line 191... |
shifter.cmd_ff <= shifter.cmd;
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shifter.cmd_ff <= shifter.cmd;
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.sreg <= opa; -- shift operand
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shifter.sreg <= opa; -- shift operand
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shifter.run = '1') then -- running shift
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elsif (shifter.run = '1') then -- running shift
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-- coarse shift -> multiples of 4 --
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-- coarse shift: multiples of 4 --
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if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
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shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
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end if;
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end if;
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-- fine shift -> 0..3 --
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-- fine shift: single shifts, 0..3 times --
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else
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else
|
shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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| Line 228... |
Line 244... |
cp_ctrl.busy <= '1';
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cp_ctrl.busy <= '1';
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.rb_ff0 <= '1';
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cp_ctrl.rb_ff0 <= '1';
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end if;
|
end if;
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else -- no co-processors implemented
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else -- no co-processor(s) implemented
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.rb_ff0 <= '0';
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cp_ctrl.rb_ff0 <= '0';
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cp_ctrl.rb_ff1 <= '0';
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cp_ctrl.rb_ff1 <= '0';
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end if;
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end if;
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| Line 248... |
Line 264... |
cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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-- ALU Function Select --------------------------------------------------------------------
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-- ALU Function Select --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter)
|
alu_function_mux: process(ctrl_i, opa, opb, add_res, sub_res, cmp_less, shifter, bitm_res)
|
begin
|
begin
|
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
|
case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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when alu_cmd_bitc_c => alu_res <= opa and (not opb); -- bit clear (for CSR modifications only)
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when alu_cmd_bitm_c => alu_res <= bitm_res;
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when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_xor_c => alu_res <= opa xor opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_or_c => alu_res <= opa or opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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when alu_cmd_and_c => alu_res <= opa and opb;
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when alu_cmd_sub_c => alu_res <= sub_res;
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when alu_cmd_sub_c => alu_res <= sub_res;
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when alu_cmd_add_c => alu_res <= add_res;
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when alu_cmd_add_c => alu_res <= add_res;
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