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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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start : std_ulogic;
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start : std_ulogic;
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run : std_ulogic;
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run : std_ulogic;
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halt : std_ulogic;
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halt : std_ulogic;
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cnt : std_ulogic_vector(4 downto 0);
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cnt : std_ulogic_vector(4 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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-- for barrel shifter only --
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bs_a_in : std_ulogic_vector(4 downto 0);
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bs_d_in : std_ulogic_vector(data_width_c-1 downto 0);
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end record;
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end record;
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signal shifter : shifter_t;
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signal shifter : shifter_t;
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-- co-processor arbiter and interface --
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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type cp_ctrl_t is record
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addsub_res <= res_v(31 downto 0);
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addsub_res <= res_v(31 downto 0);
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addsub_res <= res_v(31 downto 0);
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addsub_res <= res_v(31 downto 0);
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end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- Iterative Shifter Unit -----------------------------------------------------------------
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-- Shifter Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(rstn_i, clk_i)
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shifter_unit: process(rstn_i, clk_i)
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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shifter.sreg <= (others => '0');
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shifter.sreg <= (others => '0');
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shifter.cnt <= (others => '0');
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shifter.cnt <= (others => '0');
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shifter.cmd_ff <= '0';
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shifter.cmd_ff <= '0';
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if (FAST_SHIFT_EN = true) then
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shifter.bs_d_in <= (others => '0');
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shifter.bs_a_in <= (others => '0');
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end if;
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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shifter.cmd_ff <= shifter.cmd;
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shifter.cmd_ff <= shifter.cmd;
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-- --------------------------------------------------------------------------------
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-- Iterative shifter (small but slow) (default)
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-- --------------------------------------------------------------------------------
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if (FAST_SHIFT_EN = false) then
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.sreg <= opa; -- shift operand
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shifter.sreg <= opa; -- shift operand
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shifter.run = '1') then -- running shift
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elsif (shifter.run = '1') then -- running shift
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-- coarse shift: multiples of 4 --
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-- coarse shift: multiples of 4 --
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else -- SRL: shift right logical / SRA: shift right arithmetical
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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-- --------------------------------------------------------------------------------
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-- Barrel shifter (huge but fast)
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-- --------------------------------------------------------------------------------
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else
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-- operands and cycle control --
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if (shifter.start = '1') then -- trigger new shift
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shifter.bs_d_in <= opa; -- shift data
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= (others => '0');
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end if;
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-- convert left shifts to right shifts --
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
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bs_input_v := bit_rev_f(shifter.bs_d_in); -- reverse bit order of input operand
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else
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bs_input_v := shifter.bs_d_in;
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end if;
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-- shift >> 16 --
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if (shifter.bs_a_in(4) = '1') then
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bs_level_4_v(31 downto 16) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_4_v(15 downto 00) := (bs_input_v(31 downto 16));
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else
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bs_level_4_v := bs_input_v;
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end if;
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-- shift >> 8 --
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if (shifter.bs_a_in(3) = '1') then
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bs_level_3_v(31 downto 24) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_3_v(23 downto 00) := (bs_level_4_v(31 downto 8));
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else
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bs_level_3_v := bs_level_4_v;
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end if;
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-- shift >> 4 --
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if (shifter.bs_a_in(2) = '1') then
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bs_level_2_v(31 downto 28) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_2_v(27 downto 00) := (bs_level_3_v(31 downto 4));
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else
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bs_level_2_v := bs_level_3_v;
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end if;
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-- shift >> 2 --
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if (shifter.bs_a_in(1) = '1') then
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bs_level_1_v(31 downto 30) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_1_v(29 downto 00) := (bs_level_2_v(31 downto 2));
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else
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bs_level_1_v := bs_level_2_v;
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end if;
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-- shift >> 1 --
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if (shifter.bs_a_in(0) = '1') then
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bs_level_0_v(31 downto 31) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_0_v(30 downto 00) := (bs_level_1_v(31 downto 1));
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else
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bs_level_0_v := bs_level_1_v;
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end if;
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-- re-convert original left shifts --
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then
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shifter.sreg <= bit_rev_f(bs_level_0_v);
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else
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shifter.sreg <= bs_level_0_v;
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end if;
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end if;
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end if;
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end if;
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end process shifter_unit;
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end process shifter_unit;
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-- is shift operation? --
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-- is shift operation? --
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shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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