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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # << NEORV32 - Arithmetical/Logical Unit >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. #
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-- # Main data and address ALU. Includes comparator unit and co-processor interface/arbiter. #
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-- # The shifter sub-unit uses an iterative approach. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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opb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU operand B
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-- co-processor interface --
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-- co-processor interface --
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_start_o : out std_ulogic; -- trigger co-processor 0
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 0 result
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp0_valid_i : in std_ulogic; -- co-processor 0 result valid
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_start_o : out std_ulogic; -- trigger co-processor 1
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 1 result
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cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
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cp1_valid_i : in std_ulogic; -- co-processor 1 result valid
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cp2_start_o : out std_ulogic; -- trigger co-processor 2
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cp2_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 2 result
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cp2_valid_i : in std_ulogic; -- co-processor 2 result valid
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cp3_start_o : out std_ulogic; -- trigger co-processor 3
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cp3_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- co-processor 3 result
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cp3_valid_i : in std_ulogic; -- co-processor 3 result valid
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-- status --
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-- status --
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wait_o : out std_ulogic -- busy due to iterative processing units
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wait_o : out std_ulogic -- busy due to iterative processing units
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);
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);
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- comparator --
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal cmp_less : std_ulogic;
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-- shifter --
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-- shifter --
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type shifter_t is record
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type shifter_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand)
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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--
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opb_o <= opb;
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-- Comparator Unit ------------------------------------------------------------------------
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-- Comparator Unit ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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cmp_opx <= (rs1_i(rs1_i'left) and (not ctrl_i(ctrl_alu_unsigned_c))) & rs1_i;
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else-- addition
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else-- addition
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op_y_v := op_b_v;
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op_y_v := op_b_v;
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cin_v(0) := '0';
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cin_v(0) := '0';
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end if;
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end if;
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-- adder core --
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-- adder core (result + carry/borrow) --
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res_v := std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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addsub_res <= std_ulogic_vector(unsigned(op_a_v) + unsigned(op_y_v) + unsigned(cin_v(0 downto 0)));
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-- output --
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cmp_less <= res_v(32);
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addsub_res <= res_v(31 downto 0);
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addsub_res <= res_v(31 downto 0);
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end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- direct output of address result --
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add_o <= addsub_res(data_width_c-1 downto 0);
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-- Shifter Unit ---------------------------------------------------------------------------
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-- Shifter Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(rstn_i, clk_i)
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shifter_unit: process(clk_i)
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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begin
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if (rstn_i = '0') then
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if rising_edge(clk_i) then
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shifter.sreg <= (others => '0');
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shifter.cnt <= (others => '0');
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shifter.cmd_ff <= '0';
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if (FAST_SHIFT_EN = true) then
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shifter.bs_d_in <= (others => '0');
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shifter.bs_a_in <= (others => '0');
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end if;
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elsif rising_edge(clk_i) then
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shifter.cmd_ff <= shifter.cmd;
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shifter.cmd_ff <= shifter.cmd;
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-- --------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------
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-- Iterative shifter (small but slow) (default)
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-- Iterative shifter (small but slow) (default)
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-- --------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------
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if (FAST_SHIFT_EN = false) then
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if (FAST_SHIFT_EN = false) then
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.sreg <= opa; -- shift operand
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shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shifter.run = '1') then -- running shift
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elsif (shifter.run = '1') then -- running shift
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-- coarse shift: multiples of 4 --
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-- coarse shift: multiples of 4 --
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if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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if (or_all_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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-- --------------------------------------------------------------------------------
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-- --------------------------------------------------------------------------------
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else
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else
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-- operands and cycle control --
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-- operands and cycle control --
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if (shifter.start = '1') then -- trigger new shift
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if (shifter.start = '1') then -- trigger new shift
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shifter.bs_d_in <= opa; -- shift data
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shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= (others => '0');
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shifter.cnt <= (others => '0');
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end if;
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end if;
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-- convert left shifts to right shifts --
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-- convert left shifts to right shifts --
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_M = true) then
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if (CPU_EXTENSION_RISCV_M = true) then
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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if (cp_ctrl.start = '1') then
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if (cp_ctrl.start = '1') then
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cp_ctrl.busy <= '1';
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cp_ctrl.busy <= '1';
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elsif ((cp0_valid_i or cp1_valid_i) = '1') then -- cp computation done?
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elsif ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done?
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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end if;
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end if;
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else -- no co-processor(s) implemented
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else -- no co-processor(s) implemented
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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end process cp_arbiter;
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end process cp_arbiter;
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-- is co-processor operation? --
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-- is co-processor operation? --
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_cp_c) else '0';
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_cp_c) else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = cp_sel_muldiv_c) else '0'; -- MULDIV CP
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; -- CP0: MULDIV CP
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cp1_start_o <= '0'; -- not yet implemented
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cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; -- CP1: not implemented yet
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cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; -- CP2: not implemented yet
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cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; -- CP3: not implemented yet
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-- co-processor operation running? --
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-- co-processor operation running? --
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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-- co-processor result --
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-- co-processor result --
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cp_res <= cp0_data_i or cp1_data_i; -- only the **actaully selected** co-processor should output data != 0
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cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
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-- ALU Function Select --------------------------------------------------------------------
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, opa, opb, addsub_res, cp_res, cmp_less, shifter.sreg)
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alu_function_mux: process(ctrl_i, rs1_i, opb, addsub_res, cp_res, shifter.sreg)
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begin
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begin
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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when alu_cmd_xor_c => res_o <= opa xor opb;
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when alu_cmd_xor_c => res_o <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_cmd_or_c => res_o <= opa or opb;
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when alu_cmd_or_c => res_o <= rs1_i or opb;
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when alu_cmd_and_c => res_o <= opa and opb;
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when alu_cmd_and_c => res_o <= rs1_i and opb;
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when alu_cmd_movb_c => res_o <= opb;
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when alu_cmd_movb_c => res_o <= opb;
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when alu_cmd_addsub_c => res_o <= addsub_res;
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when alu_cmd_addsub_c => res_o <= addsub_res(data_width_c-1 downto 0);
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when alu_cmd_cp_c => res_o <= cp_res;
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when alu_cmd_cp_c => res_o <= cp_res;
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when alu_cmd_shift_c => res_o <= shifter.sreg;
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when alu_cmd_shift_c => res_o <= shifter.sreg;
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when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= cmp_less;
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when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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when others => res_o <= opb; -- undefined
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when others => res_o <= opb; -- undefined
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end case;
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end case;
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end process alu_function_mux;
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end process alu_function_mux;
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