| Line 84... |
Line 84... |
-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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--
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- comparator --
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-- comparator --
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opx : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_opy : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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signal cmp_sub : std_ulogic_vector(data_width_c downto 0);
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| Line 165... |
Line 168... |
end process binary_arithmetic_core;
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end process binary_arithmetic_core;
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-- direct output of address result --
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-- direct output of address result --
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add_o <= addsub_res(data_width_c-1 downto 0);
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add_o <= addsub_res(data_width_c-1 downto 0);
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-- ALU arithmetic logic core --
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arithmetic_core: process(ctrl_i, addsub_res)
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begin
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if (ctrl_i(ctrl_alu_arith_c) = alu_arith_cmd_addsub_c) then -- ADD/SUB
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arith_res <= addsub_res(data_width_c-1 downto 0);
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else -- SLT
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arith_res <= (others => '0');
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arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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end if;
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end process arithmetic_core;
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-- Shifter Unit ---------------------------------------------------------------------------
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-- Shifter Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(clk_i)
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shifter_unit: process(clk_i)
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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| Line 274... |
Line 288... |
end if;
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end if;
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end if;
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end if;
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end process shifter_unit;
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end process shifter_unit;
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-- is shift operation? --
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-- is shift operation? --
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shifter.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_shift_c) else '0';
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shifter.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_shift_c) else '0';
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shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
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shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
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-- shift operation running? --
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-- shift operation running? --
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shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
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shifter.run <= '1' when (or_all_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
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shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
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shifter.halt <= '1' when (or_all_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
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| Line 292... |
Line 306... |
cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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if (CPU_EXTENSION_RISCV_M = true) then
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if (CPU_EXTENSION_RISCV_M = true) then
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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if (cp_ctrl.start = '1') then
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if ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done?
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cp_ctrl.busy <= '1';
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elsif ((cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i) = '1') then -- cp computation done?
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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elsif (cp_ctrl.start = '1') then
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cp_ctrl.busy <= '1';
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end if;
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end if;
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else -- no co-processor(s) implemented
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else -- no co-processor(s) implemented
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process cp_arbiter;
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end process cp_arbiter;
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-- is co-processor operation? --
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-- is co-processor operation? --
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) = alu_cmd_cp_c) else '0';
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0'; -- CP0: MULDIV CP
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cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0'; -- CP1: not implemented yet
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cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0'; -- CP2: not implemented yet
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cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0'; -- CP3: not implemented yet
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-- co-processor operation running? --
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-- co-processor select --
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cp_ctrl.halt <= cp_ctrl.busy or cp_ctrl.start;
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cp0_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
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cp1_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
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cp2_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
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cp3_start_o <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
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-- co-processor operation (still) running? --
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cp_ctrl.halt <= (cp_ctrl.busy and (not (cp0_valid_i or cp1_valid_i or cp2_valid_i or cp3_valid_i))) or cp_ctrl.start;
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-- co-processor result --
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-- co-processor result --
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cp_read_back: process(clk_i)
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begin
|
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if rising_edge(clk_i) then
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cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
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cp_res <= cp0_data_i or cp1_data_i or cp2_data_i or cp3_data_i; -- only the *actually selected* co-processor may output data != 0
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end if;
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end process cp_read_back;
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-- ALU Logic Core -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_logic_core: process(ctrl_i, rs1_i, opb)
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begin
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case ctrl_i(ctrl_alu_logic1_c downto ctrl_alu_logic0_c) is
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when alu_logic_cmd_movb_c => logic_res <= opb; -- (default)
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when alu_logic_cmd_xor_c => logic_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_logic_cmd_or_c => logic_res <= rs1_i or opb;
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when alu_logic_cmd_and_c => logic_res <= rs1_i and opb;
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when others => logic_res <= opb; -- undefined
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end case;
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end process alu_logic_core;
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-- ALU Function Select --------------------------------------------------------------------
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, rs1_i, opb, addsub_res, cp_res, shifter.sreg)
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alu_function_mux: process(ctrl_i, arith_res, logic_res, shifter.sreg, cp_res)
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begin
|
begin
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case ctrl_i(ctrl_alu_cmd2_c downto ctrl_alu_cmd0_c) is
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case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
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when alu_cmd_xor_c => res_o <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
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when alu_cmd_or_c => res_o <= rs1_i or opb;
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when alu_func_cmd_logic_c => res_o <= logic_res;
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when alu_cmd_and_c => res_o <= rs1_i and opb;
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when alu_func_cmd_shift_c => res_o <= shifter.sreg;
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when alu_cmd_movb_c => res_o <= opb;
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when alu_func_cmd_copro_c => res_o <= cp_res;
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when alu_cmd_addsub_c => res_o <= addsub_res(data_width_c-1 downto 0);
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when others => res_o <= arith_res; -- undefined
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when alu_cmd_cp_c => res_o <= cp_res;
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when alu_cmd_shift_c => res_o <= shifter.sreg;
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when alu_cmd_slt_c => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- => carry/borrow
|
|
when others => res_o <= opb; -- undefined
|
|
end case;
|
end case;
|
end process alu_function_mux;
|
end process alu_function_mux;
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|
-- ALU Busy -------------------------------------------------------------------------------
|
-- ALU Busy -------------------------------------------------------------------------------
|
