| Line 41... |
Line 41... |
library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
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-- RISC-V CPU Extensions --
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FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension?
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TINY_SHIFT_EN : boolean := false -- use tiny (single-bit) shifter for shift operations
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CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
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-- Extension Options --
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FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean := false -- use barrel shifter for shift operations
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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| Line 55... |
Line 59... |
-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
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-- data output --
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-- data output --
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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-- co-processor interface --
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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cp_start_o : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
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cp_valid_i : in std_ulogic_vector(7 downto 0); -- co-processor i done
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cp_result_i : in cp_data_if_t; -- co-processor result
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-- status --
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-- status --
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wait_o : out std_ulogic -- busy due to iterative processing units
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idone_o : out std_ulogic -- iterative processing units done?
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);
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);
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end neorv32_cpu_alu;
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end neorv32_cpu_alu;
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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architecture neorv32_cpu_cpu_rtl of neorv32_cpu_alu is
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| Line 79... |
Line 82... |
--
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--
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal arith_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal logic_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- shifter --
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type shifter_t is record
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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start : std_ulogic;
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run : std_ulogic;
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halt : std_ulogic;
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cnt : std_ulogic_vector(4 downto 0);
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sreg : std_ulogic_vector(data_width_c-1 downto 0);
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-- for barrel shifter only --
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bs_a_in : std_ulogic_vector(4 downto 0);
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bs_d_in : std_ulogic_vector(data_width_c-1 downto 0);
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end record;
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signal shifter : shifter_t;
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-- co-processor arbiter and interface --
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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type cp_ctrl_t is record
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cmd : std_ulogic;
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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cmd_ff : std_ulogic;
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busy : std_ulogic;
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start : std_ulogic;
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start : std_ulogic;
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halt : std_ulogic;
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busy : std_ulogic;
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timeout : std_ulogic_vector(9 downto 0);
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timeout : std_ulogic_vector(9 downto 0);
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end record;
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end record;
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signal cp_ctrl : cp_ctrl_t;
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signal cp_ctrl : cp_ctrl_t;
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-- co-processor interface --
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signal cp_start : std_ulogic_vector(3 downto 0); -- trigger co-processor i
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signal cp_valid : std_ulogic_vector(3 downto 0); -- co-processor i done
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signal cp_result : cp_data_if_t; -- co-processor result
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begin
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begin
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-- Operand Mux ----------------------------------------------------------------------------
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-- Operand Mux ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opa <= pc2_i when (ctrl_i(ctrl_alu_opa_mux_c) = '1') else rs1_i; -- operand a (first ALU input operand), only required for arithmetic ops
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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opb <= imm_i when (ctrl_i(ctrl_alu_opb_mux_c) = '1') else rs2_i; -- operand b (second ALU input operand)
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-- Binary Adder/Subtractor ----------------------------------------------------------------
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-- Binary Adder/Subtracter ----------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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binary_arithmetic_core: process(ctrl_i, opa, opb)
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable cin_v : std_ulogic_vector(0 downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable op_a_v : std_ulogic_vector(data_width_c downto 0);
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variable op_b_v : std_ulogic_vector(data_width_c downto 0);
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variable op_b_v : std_ulogic_vector(data_width_c downto 0);
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| Line 152... |
Line 144... |
arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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arith_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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end if;
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end if;
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end process arithmetic_core;
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end process arithmetic_core;
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-- Shifter Unit ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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shifter_unit: process(clk_i)
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variable bs_input_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_4_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_3_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_2_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_1_v : std_ulogic_vector(data_width_c-1 downto 0);
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variable bs_level_0_v : std_ulogic_vector(data_width_c-1 downto 0);
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begin
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if rising_edge(clk_i) then
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shifter.cmd_ff <= shifter.cmd;
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-- --------------------------------------------------------------------------------
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-- Iterative shifter (small but slow) (default)
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-- --------------------------------------------------------------------------------
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if (FAST_SHIFT_EN = false) then
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if (shifter.start = '1') then -- trigger new shift
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shifter.sreg <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.cnt <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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elsif (shifter.run = '1') then -- running shift
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-- coarse shift: multiples of 4 --
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if (TINY_SHIFT_EN = false) and -- use coarse shifts first if TINY SHIFT option is NOT enabled
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(or_reduce_f(shifter.cnt(shifter.cnt'left downto 2)) = '1') then -- shift amount >= 4
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 4);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-4 downto 0) & "0000";
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) &
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(shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 4);
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end if;
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-- fine shift: single shifts, 0..3 times; use ONLY single-bit shifts if TINY_SHIFT_EN is enabled (even smaller than the default approach) --
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else
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shifter.cnt <= std_ulogic_vector(unsigned(shifter.cnt) - 1);
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- SLL: shift left logical
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shifter.sreg <= shifter.sreg(shifter.sreg'left-1 downto 0) & '0';
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else -- SRL: shift right logical / SRA: shift right arithmetical
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shifter.sreg <= (shifter.sreg(shifter.sreg'left) and ctrl_i(ctrl_alu_shift_ar_c)) & shifter.sreg(shifter.sreg'left downto 1);
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end if;
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end if;
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end if;
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-- --------------------------------------------------------------------------------
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-- Barrel shifter (huge but fast)
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-- --------------------------------------------------------------------------------
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else
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-- operands and cycle control --
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if (shifter.start = '1') then -- trigger new shift
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shifter.bs_d_in <= rs1_i; -- shift operand (can only be rs1; opa would also contain pc)
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shifter.bs_a_in <= opb(index_size_f(data_width_c)-1 downto 0); -- shift amount
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shifter.cnt <= (others => '0');
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end if;
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-- convert left shifts to right shifts --
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then -- is left shift?
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bs_input_v := bit_rev_f(shifter.bs_d_in); -- reverse bit order of input operand
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else
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bs_input_v := shifter.bs_d_in;
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end if;
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-- shift >> 16 --
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if (shifter.bs_a_in(4) = '1') then
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bs_level_4_v(31 downto 16) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_4_v(15 downto 00) := (bs_input_v(31 downto 16));
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else
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bs_level_4_v := bs_input_v;
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end if;
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-- shift >> 8 --
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if (shifter.bs_a_in(3) = '1') then
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bs_level_3_v(31 downto 24) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_3_v(23 downto 00) := (bs_level_4_v(31 downto 8));
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else
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bs_level_3_v := bs_level_4_v;
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end if;
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-- shift >> 4 --
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if (shifter.bs_a_in(2) = '1') then
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bs_level_2_v(31 downto 28) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_2_v(27 downto 00) := (bs_level_3_v(31 downto 4));
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else
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bs_level_2_v := bs_level_3_v;
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end if;
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-- shift >> 2 --
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if (shifter.bs_a_in(1) = '1') then
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bs_level_1_v(31 downto 30) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_1_v(29 downto 00) := (bs_level_2_v(31 downto 2));
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else
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bs_level_1_v := bs_level_2_v;
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end if;
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-- shift >> 1 --
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if (shifter.bs_a_in(0) = '1') then
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bs_level_0_v(31 downto 31) := (others => (bs_input_v(bs_input_v'left) and ctrl_i(ctrl_alu_shift_ar_c)));
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bs_level_0_v(30 downto 00) := (bs_level_1_v(31 downto 1));
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else
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bs_level_0_v := bs_level_1_v;
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end if;
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-- re-convert original left shifts --
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if (ctrl_i(ctrl_alu_shift_dir_c) = '0') then
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shifter.sreg <= bit_rev_f(bs_level_0_v);
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else
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shifter.sreg <= bs_level_0_v;
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end if;
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end if;
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end if;
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end process shifter_unit;
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-- is shift operation? --
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shifter.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_shift_c) else '0';
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shifter.start <= '1' when (shifter.cmd = '1') and (shifter.cmd_ff = '0') else '0';
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-- shift operation running? --
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shifter.run <= '1' when (or_reduce_f(shifter.cnt) = '1') or (shifter.start = '1') else '0';
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shifter.halt <= '1' when (or_reduce_f(shifter.cnt(shifter.cnt'left downto 1)) = '1') or (shifter.start = '1') else '0';
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-- Co-Processor Arbiter -------------------------------------------------------------------
|
-- Co-Processor Arbiter -------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- Interface:
|
-- Interface:
|
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
|
-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
|
-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
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| Line 281... |
Line 157... |
cp_ctrl.cmd_ff <= '0';
|
cp_ctrl.cmd_ff <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.busy <= '0';
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cp_ctrl.timeout <= (others => '0');
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cp_ctrl.timeout <= (others => '0');
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
|
cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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if (or_reduce_f(cp_valid_i) = '1') then -- cp computation done?
|
-- timeout counter --
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cp_ctrl.busy <= '0';
|
if (cp_ctrl.start = '1') then
|
elsif (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
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assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
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cp_ctrl.busy <= '0';
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elsif (cp_ctrl.start = '1') then
|
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cp_ctrl.busy <= '1';
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cp_ctrl.busy <= '1';
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elsif (or_reduce_f(cp_valid) = '1') then
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cp_ctrl.busy <= '0';
|
end if;
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end if;
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-- timeout counter --
|
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if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
|
if (cp_ctrl.busy = '1') and (cp_timeout_en_c = true) then
|
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
|
cp_ctrl.timeout <= std_ulogic_vector(unsigned(cp_ctrl.timeout) + 1);
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else
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else
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cp_ctrl.timeout <= (others => '0');
|
cp_ctrl.timeout <= (others => '0');
|
end if;
|
end if;
|
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if (cp_ctrl.timeout(cp_ctrl.timeout'left) = '1') and (cp_timeout_en_c = true) then -- timeout
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assert false report "NEORV32 CPU CO-PROCESSOR TIMEOUT ERROR!" severity warning;
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end if;
|
end if;
|
end if;
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end process cp_arbiter;
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end process cp_arbiter;
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|
|
-- is co-processor operation? --
|
-- is co-processor operation? --
|
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
|
cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_cmd_copro_c) else '0';
|
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
|
cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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|
|
-- co-processor select --
|
-- co-processor select / star trigger --
|
cp_operation_trigger: process(cp_ctrl, ctrl_i)
|
cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "00") else '0';
|
begin
|
cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "01") else '0';
|
for i in 0 to 7 loop
|
cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "10") else '0';
|
if (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = std_ulogic_vector(to_unsigned(i, 3))) then
|
cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "11") else '0';
|
cp_start_o(i) <= '1';
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else
|
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cp_start_o(i) <= '0';
|
|
end if;
|
|
end loop; -- i
|
|
end process;
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|
|
|
-- co-processor operation (still) running? --
|
-- co-processor operation done? --
|
cp_ctrl.halt <= (cp_ctrl.busy and (not or_reduce_f(cp_valid_i))) or cp_ctrl.start;
|
idone_o <= or_reduce_f(cp_valid);
|
|
|
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
|
-- co-processor result - only the *actually selected* co-processor may output data != 0 --
|
cp_res <= cp_result_i(0) or cp_result_i(1) or cp_result_i(2) or cp_result_i(3) or
|
cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3);
|
cp_result_i(4) or cp_result_i(5) or cp_result_i(6) or cp_result_i(7);
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|
|
|
|
|
-- ALU Logic Core -------------------------------------------------------------------------
|
-- ALU Logic Core -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_logic_core: process(ctrl_i, rs1_i, opb)
|
alu_logic_core: process(ctrl_i, rs1_i, opb)
|
| Line 338... |
Line 207... |
end process alu_logic_core;
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end process alu_logic_core;
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|
|
|
|
-- ALU Function Select --------------------------------------------------------------------
|
-- ALU Function Select --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
alu_function_mux: process(ctrl_i, arith_res, logic_res, shifter.sreg, cp_res)
|
alu_function_mux: process(ctrl_i, arith_res, logic_res, csr_i, cp_res)
|
begin
|
begin
|
case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
|
case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
|
when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
|
when alu_func_cmd_arith_c => res_o <= arith_res; -- (default)
|
when alu_func_cmd_logic_c => res_o <= logic_res;
|
when alu_func_cmd_logic_c => res_o <= logic_res;
|
when alu_func_cmd_shift_c => res_o <= shifter.sreg;
|
when alu_func_cmd_csrr_c => res_o <= csr_i;
|
when alu_func_cmd_copro_c => res_o <= cp_res;
|
when alu_func_cmd_copro_c => res_o <= cp_res;
|
when others => res_o <= arith_res; -- undefined
|
when others => res_o <= arith_res; -- undefined
|
end case;
|
end case;
|
end process alu_function_mux;
|
end process alu_function_mux;
|
|
|
|
|
-- ALU Busy -------------------------------------------------------------------------------
|
-- **************************************************************************************************************************
|
|
-- Co-Processors
|
|
-- **************************************************************************************************************************
|
|
|
|
-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
|
|
generic map (
|
|
FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
|
|
)
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl_i, -- main control bus
|
|
start_i => cp_start(0), -- trigger operation
|
|
-- data input --
|
|
rs1_i => rs1_i, -- rf source 1
|
|
rs2_i => rs2_i, -- rf source 2
|
|
imm_i => imm_i, -- immediate
|
|
-- result and status --
|
|
res_o => cp_result(0), -- operation result
|
|
valid_o => cp_valid(0) -- data output valid
|
|
);
|
|
|
|
|
|
-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_cpu_cp_muldiv_inst_true:
|
|
if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
|
|
neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
|
|
generic map (
|
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for faster multiplication
|
|
DIVISION_EN => CPU_EXTENSION_RISCV_M -- implement divider hardware
|
|
)
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl_i, -- main control bus
|
|
start_i => cp_start(1), -- trigger operation
|
|
-- data input --
|
|
rs1_i => rs1_i, -- rf source 1
|
|
rs2_i => rs2_i, -- rf source 2
|
|
-- result and status --
|
|
res_o => cp_result(1), -- operation result
|
|
valid_o => cp_valid(1) -- data output valid
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_cp_muldiv_inst_false:
|
|
if (CPU_EXTENSION_RISCV_M = false) and (CPU_EXTENSION_RISCV_Zmmul = false) generate
|
|
cp_result(1) <= (others => '0');
|
|
cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
|
|
end generate;
|
|
|
|
|
|
-- Co-Processor 2: reserved ---------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
cp_result(2) <= (others => '0');
|
|
cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
|
|
|
|
|
|
-- Co-Processor 3: Single-Precision Floating-Point Unit ('Zfinx' Extension) ---------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
wait_o <= shifter.halt or cp_ctrl.halt; -- wait until iterative units have completed
|
neorv32_cpu_cp_fpu_inst_true:
|
|
if (CPU_EXTENSION_RISCV_Zfinx = true) generate
|
|
neorv32_cpu_cp_fpu_inst: neorv32_cpu_cp_fpu
|
|
port map (
|
|
-- global control --
|
|
clk_i => clk_i, -- global clock, rising edge
|
|
rstn_i => rstn_i, -- global reset, low-active, async
|
|
ctrl_i => ctrl_i, -- main control bus
|
|
start_i => cp_start(3), -- trigger operation
|
|
-- data input --
|
|
cmp_i => cmp_i, -- comparator status
|
|
rs1_i => rs1_i, -- rf source 1
|
|
rs2_i => rs2_i, -- rf source 2
|
|
-- result and status --
|
|
res_o => cp_result(3), -- operation result
|
|
fflags_o => fpu_flags_o, -- exception flags
|
|
valid_o => cp_valid(3) -- data output valid
|
|
);
|
|
end generate;
|
|
|
|
neorv32_cpu_cp_fpu_inst_false:
|
|
if (CPU_EXTENSION_RISCV_Zfinx = false) generate
|
|
cp_result(3) <= (others => '0');
|
|
fpu_flags_o <= (others => '0');
|
|
cp_valid(3) <= cp_start(3); -- to make sure CPU does not get stalled if there is an accidental access
|
|
end generate;
|
|
|
|
|
end neorv32_cpu_cpu_rtl;
|
end neorv32_cpu_cpu_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
