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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_alu is
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entity neorv32_cpu_alu is
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generic (
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generic (
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_B : boolean; -- implement bit-manipulation extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_M : boolean; -- implement mul/div extension?
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CPU_EXTENSION_RISCV_Zbb : boolean; -- implement basic bit-manipulation sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
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-- Extension Options --
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-- Extension Options --
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_MUL_EN : boolean; -- use DSPs for M extension's multiplier
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FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
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FAST_SHIFT_EN : boolean -- use barrel shifter for shift operations
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rstn_i => rstn_i, -- global reset, low-active, async
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rstn_i => rstn_i, -- global reset, low-active, async
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ctrl_i => ctrl_i, -- main control bus
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ctrl_i => ctrl_i, -- main control bus
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start_i => cp_start(0), -- trigger operation
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start_i => cp_start(0), -- trigger operation
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-- data input --
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-- data input --
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rs1_i => rs1_i, -- rf source 1
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rs1_i => rs1_i, -- rf source 1
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rs2_i => rs2_i, -- rf source 2
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shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount
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imm_i => imm_i, -- immediate
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-- result and status --
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-- result and status --
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res_o => cp_result(0), -- operation result
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res_o => cp_result(0), -- operation result
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valid_o => cp_valid(0) -- data output valid
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valid_o => cp_valid(0) -- data output valid
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);
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);
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cp_result(1) <= (others => '0');
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cp_result(1) <= (others => '0');
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cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
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cp_valid(1) <= cp_start(1); -- to make sure CPU does not get stalled if there is an accidental access
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end generate;
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end generate;
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-- Co-Processor 2: Bit-Manipulation Unit ('B'/'Zbb' Extension) ----------------------------
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-- Co-Processor 2: Bit-Manipulation Unit ('B' Extension) ----------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_bitmanip_inst_true:
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neorv32_cpu_cp_bitmanip_inst_true:
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if (CPU_EXTENSION_RISCV_Zbb = true) generate
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if (CPU_EXTENSION_RISCV_B = true) generate
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neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
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neorv32_cpu_cp_bitmanip_inst: neorv32_cpu_cp_bitmanip
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generic map (
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generic map (
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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)
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)
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port map (
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port map (
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start_i => cp_start(2), -- trigger operation
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start_i => cp_start(2), -- trigger operation
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-- data input --
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-- data input --
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cmp_i => cmp, -- comparator status
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cmp_i => cmp, -- comparator status
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rs1_i => rs1_i, -- rf source 1
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rs1_i => rs1_i, -- rf source 1
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rs2_i => rs2_i, -- rf source 2
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rs2_i => rs2_i, -- rf source 2
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shamt_i => opb(index_size_f(data_width_c)-1 downto 0), -- shift amount
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-- result and status --
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-- result and status --
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res_o => cp_result(2), -- operation result
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res_o => cp_result(2), -- operation result
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valid_o => cp_valid(2) -- data output valid
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valid_o => cp_valid(2) -- data output valid
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);
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);
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end generate;
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end generate;
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neorv32_cpu_cp_bitmanip_inst_false:
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neorv32_cpu_cp_bitmanip_inst_false:
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if (CPU_EXTENSION_RISCV_Zbb = false) generate
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if (CPU_EXTENSION_RISCV_B = false) generate
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cp_result(2) <= (others => '0');
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cp_result(2) <= (others => '0');
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cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
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cp_valid(2) <= cp_start(2); -- to make sure CPU does not get stalled if there is an accidental access
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end generate;
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end generate;
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