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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_alu.vhd] - Diff between revs 71 and 72

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-- #################################################################################################
-- #################################################################################################
-- # << NEORV32 - Arithmetical/Logical Unit >>                                                     #
-- # << NEORV32 - Arithmetical/Logical Unit >>                                                     #
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # Main data and address ALU and co-processor interface/arbiter.                                 #
-- # Main data/address ALU and ALU co-processor (= multi-cycle function units).                    #
-- # ********************************************************************************************* #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License                                                                          #
-- # BSD 3-Clause License                                                                          #
-- #                                                                                               #
-- #                                                                                               #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
-- # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
-- #                                                                                               #
-- #                                                                                               #
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    -- RISC-V CPU Extensions --
    -- RISC-V CPU Extensions --
    CPU_EXTENSION_RISCV_B     : boolean; -- implement bit-manipulation extension?
    CPU_EXTENSION_RISCV_B     : boolean; -- implement bit-manipulation extension?
    CPU_EXTENSION_RISCV_M     : boolean; -- implement mul/div extension?
    CPU_EXTENSION_RISCV_M     : boolean; -- implement mul/div extension?
    CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
    CPU_EXTENSION_RISCV_Zmmul : boolean; -- implement multiply-only M sub-extension?
    CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
    CPU_EXTENSION_RISCV_Zfinx : boolean; -- implement 32-bit floating-point extension (using INT reg!)
 
    CPU_EXTENSION_RISCV_Zxcfu : boolean; -- implement custom (instr.) functions unit?
    -- Extension Options --
    -- Extension Options --
    FAST_MUL_EN               : boolean; -- use DSPs for M extension's multiplier
    FAST_MUL_EN               : boolean; -- use DSPs for M extension's multiplier
    FAST_SHIFT_EN             : boolean  -- use barrel shifter for shift operations
    FAST_SHIFT_EN             : boolean  -- use barrel shifter for shift operations
  );
  );
  port (
  port (
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    fpu_flags_o  <= (others => '0');
    fpu_flags_o  <= (others => '0');
    cp_valid(3)  <= '0';
    cp_valid(3)  <= '0';
  end generate;
  end generate;
 
 
 
 
  -- Co-Processor 4: Reserved ---------------------------------------------------------------
  -- Co-Processor 4: Custom (Instructions) Functions Unit ('Zxcfu' Extension) ---------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
 
  neorv32_cpu_cp_cfu_inst_true:
 
  if (CPU_EXTENSION_RISCV_Zxcfu = true) generate
 
    neorv32_cpu_cp_cfu_inst: neorv32_cpu_cp_cfu
 
    port map (
 
      -- global control --
 
      clk_i   => clk_i,        -- global clock, rising edge
 
      rstn_i  => rstn_i,       -- global reset, low-active, async
 
      ctrl_i  => ctrl_i,       -- main control bus
 
      start_i => cp_start(4),  -- trigger operation
 
      -- data input --
 
      rs1_i   => rs1_i,        -- rf source 1
 
      rs2_i   => rs2_i,        -- rf source 2
 
      -- result and status --
 
      res_o   => cp_result(4), -- operation result
 
      valid_o => cp_valid(4)   -- data output valid
 
    );
 
  end generate;
 
 
 
  neorv32_cpu_cp_cfu_inst_false:
 
  if (CPU_EXTENSION_RISCV_Zxcfu = false) generate
  cp_result(4) <= (others => '0');
  cp_result(4) <= (others => '0');
  cp_valid(4)  <= '0';
  cp_valid(4)  <= '0';
 
  end generate;
 
 
 
 
  -- Co-Processor 5: Reserved ---------------------------------------------------------------
  -- Co-Processor 5: Reserved ---------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  cp_result(5) <= (others => '0');
  cp_result(5) <= (others => '0');

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