| Line 60... |
Line 60... |
ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
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-- data input --
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-- data input --
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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pc_i : in std_ulogic_vector(data_width_c-1 downto 0); -- current PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- next PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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-- data output --
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-- data output --
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
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-- operands --
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-- operands --
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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signal opa, opb : std_ulogic_vector(data_width_c-1 downto 0);
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-- results --
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-- results --
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal addsub_res : std_ulogic_vector(data_width_c downto 0);
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signal alu_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_res : std_ulogic_vector(data_width_c-1 downto 0);
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-- co-processor arbiter and interface --
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type cp_ctrl_t is record
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cmd : std_ulogic;
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cmd_ff : std_ulogic;
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start : std_ulogic;
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end record;
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signal cp_ctrl : cp_ctrl_t;
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-- co-processor interface --
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-- co-processor interface --
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type cp_data_if_t is array (0 to 7) of std_ulogic_vector(data_width_c-1 downto 0);
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type cp_data_if_t is array (0 to 7) of std_ulogic_vector(data_width_c-1 downto 0);
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signal cp_result : cp_data_if_t; -- co-processor result
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signal cp_result : cp_data_if_t; -- co-processor i result
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signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
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signal cp_start : std_ulogic_vector(7 downto 0); -- trigger co-processor i
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signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
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signal cp_valid : std_ulogic_vector(7 downto 0); -- co-processor i done
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begin
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begin
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add_o <= addsub_res(data_width_c-1 downto 0);
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add_o <= addsub_res(data_width_c-1 downto 0);
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-- ALU Operation Select -------------------------------------------------------------------
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-- ALU Operation Select -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_core: process(ctrl_i, addsub_res, rs1_i, opb)
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alu_core: process(ctrl_i, addsub_res, cp_res, rs1_i, opb)
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begin
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begin
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case ctrl_i(ctrl_alu_op2_c downto ctrl_alu_op0_c) is
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case ctrl_i(ctrl_alu_op2_c downto ctrl_alu_op0_c) is
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when alu_op_add_c => alu_res <= addsub_res(data_width_c-1 downto 0); -- (default)
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when alu_op_add_c => res_o <= addsub_res(data_width_c-1 downto 0); -- default
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when alu_op_sub_c => alu_res <= addsub_res(data_width_c-1 downto 0);
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when alu_op_sub_c => res_o <= addsub_res(data_width_c-1 downto 0);
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-- when alu_op_mova_c => alu_res <= rs1_i; -- FIXME
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when alu_op_cp_c => res_o <= cp_res;
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when alu_op_slt_c => alu_res <= (others => '0'); alu_res(0) <= addsub_res(addsub_res'left); -- => carry/borrow
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when alu_op_slt_c => res_o <= (others => '0'); res_o(0) <= addsub_res(addsub_res'left); -- carry/borrow
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when alu_op_movb_c => alu_res <= opb;
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when alu_op_movb_c => res_o <= opb;
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when alu_op_xor_c => alu_res <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_op_xor_c => res_o <= rs1_i xor opb; -- only rs1 required for logic ops (opa would also contain pc)
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when alu_op_or_c => alu_res <= rs1_i or opb;
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when alu_op_or_c => res_o <= rs1_i or opb;
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when alu_op_and_c => alu_res <= rs1_i and opb;
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when alu_op_and_c => res_o <= rs1_i and opb;
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when others => alu_res <= addsub_res(data_width_c-1 downto 0);
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when others => res_o <= addsub_res(data_width_c-1 downto 0);
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end case;
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end case;
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end process alu_core;
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end process alu_core;
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-- ALU Function Select --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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alu_function_mux: process(ctrl_i, alu_res, pc2_i, csr_i, cp_res)
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begin
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case ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) is
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when alu_func_core_c => res_o <= alu_res; -- (default)
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when alu_func_nxpc_c => res_o <= pc2_i;
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when alu_func_csrr_c => res_o <= csr_i;
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when alu_func_copro_c => res_o <= cp_res;
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when others => res_o <= alu_res; -- undefined
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end case;
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end process alu_function_mux;
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-- **************************************************************************************************************************
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-- **************************************************************************************************************************
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-- CPU Co-Processors
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-- ALU Co-Processors
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-- **************************************************************************************************************************
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-- **************************************************************************************************************************
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-- Co-Processor Interface --
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-- Co-processor "valid" signal has to be asserted (for one cycle) one cycle before asserting output data
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-- Co-processor "output data" has to be always zero unless co-processor was explicitly triggered
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-- Co-Processor Arbiter -------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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cp_arbiter: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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cp_ctrl.cmd_ff <= '0';
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elsif rising_edge(clk_i) then
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cp_ctrl.cmd_ff <= cp_ctrl.cmd;
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end if;
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end process cp_arbiter;
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-- is co-processor operation? --
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cp_ctrl.cmd <= '1' when (ctrl_i(ctrl_alu_func1_c downto ctrl_alu_func0_c) = alu_func_copro_c) else '0';
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cp_ctrl.start <= '1' when (cp_ctrl.cmd = '1') and (cp_ctrl.cmd_ff = '0') else '0';
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-- co-processor select / start trigger --
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-- co-processor select / start trigger --
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cp_start(0) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "000") else '0';
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-- > "cp_start" is high for one cycle to trigger operation of the according co-processor
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cp_start(1) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "001") else '0';
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cp_start(7 downto 0) <= ctrl_i(ctrl_cp_trig7_c downto ctrl_cp_trig0_c);
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cp_start(2) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "010") else '0';
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cp_start(3) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "011") else '0';
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cp_start(4) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "100") else '0';
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cp_start(5) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "101") else '0';
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cp_start(6) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "110") else '0';
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cp_start(7) <= '1' when (cp_ctrl.start = '1') and (ctrl_i(ctrl_cp_id_msb_c downto ctrl_cp_id_lsb_c) = "111") else '0';
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-- co-processor operation done? --
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-- co-processor operation done? --
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idone_o <= or_reduce_f(cp_valid);
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-- > "cp_valid" signal has to be set (for one cycle) one cycle before output data (cp_result) is valid
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idone_o <= cp_valid(0) or cp_valid(1) or cp_valid(2) or cp_valid(3) or
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cp_valid(4) or cp_valid(5) or cp_valid(6) or cp_valid(7);
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-- co-processor result - only the *actually selected* co-processor may output data != 0 --
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-- co-processor result --
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cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or cp_result(4) or cp_result(5) or cp_result(6) or cp_result(7);
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-- > "cp_result" data has to be always zero unless co-processor was actually triggered
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cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or
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cp_result(4) or cp_result(5) or cp_result(6) or cp_result(7);
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-- Co-Processor 0: Shifter (CPU Core ISA) --------------------------------------------------
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-- Co-Processor 0: Shifter Unit (CPU Base ISA) --------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
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neorv32_cpu_cp_shifter_inst: neorv32_cpu_cp_shifter
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generic map (
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generic map (
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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FAST_SHIFT_EN => FAST_SHIFT_EN -- use barrel shifter for shift operations
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)
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)
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| Line 240... |
Line 195... |
res_o => cp_result(0), -- operation result
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res_o => cp_result(0), -- operation result
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valid_o => cp_valid(0) -- data output valid
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valid_o => cp_valid(0) -- data output valid
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);
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);
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-- Co-Processor 1: Integer Multiplication/Division ('M' Extension) ------------------------
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-- Co-Processor 1: Integer Multiplication/Division Unit ('M' Extension) -------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cpu_cp_muldiv_inst_true:
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neorv32_cpu_cp_muldiv_inst_true:
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if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
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if (CPU_EXTENSION_RISCV_M = true) or (CPU_EXTENSION_RISCV_Zmmul = true) generate
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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neorv32_cpu_cp_muldiv_inst: neorv32_cpu_cp_muldiv
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generic map (
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generic map (
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