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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_bus is
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entity neorv32_cpu_bus is
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generic (
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generic (
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
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BUS_TIMEOUT : natural := 15 -- cycles after which a valid bus access will timeout
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BUS_TIMEOUT : natural := 15; -- cycles after which a valid bus access will timeout
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-- Physical memory protection (PMP) --
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PMP_USE : boolean := false; -- implement physical memory protection?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (1..4)
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PMP_GRANULARITY : natural := 16 -- granularity (0=none, 1=8B, 2=16B, 3=32B, ...)
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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rstn_i : in std_ulogic; -- global reset, low-active, async
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--
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--
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_load_o : out std_ulogic; -- misaligned load data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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ma_store_o : out std_ulogic; -- misaligned store data address
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be_load_o : out std_ulogic; -- bus error on load data access
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be_load_o : out std_ulogic; -- bus error on load data access
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be_store_o : out std_ulogic; -- bus error on store data access
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be_store_o : out std_ulogic; -- bus error on store data access
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-- physical memory protection --
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pmp_addr_i : in pmp_addr_if_t; -- addresses
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pmp_maddr_o : out pmp_addr_if_t; -- masked addresses
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pmp_ctrl_i : in pmp_ctrl_if_t; -- configs
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priv_mode_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- instruction bus --
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-- instruction bus --
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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);
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);
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end neorv32_cpu_bus;
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end neorv32_cpu_bus;
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
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-- PMP modes --
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constant pmp_off_mode_c : std_ulogic_vector(1 downto 0) := "00"; -- null region (disabled)
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constant pmp_tor_mode_c : std_ulogic_vector(1 downto 0) := "01"; -- top of range
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constant pmp_na4_mode_c : std_ulogic_vector(1 downto 0) := "10"; -- naturally aligned four-byte region
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constant pmp_napot_mode_c : std_ulogic_vector(1 downto 0) := "11"; -- naturally aligned power-of-two region (>= 8 bytes)
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-- PMP configuration register bits --
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constant pmp_cfg_r_c : natural := 0; -- read permit
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constant pmp_cfg_w_c : natural := 1; -- write permit
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constant pmp_cfg_x_c : natural := 2; -- execute permit
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constant pmp_cfg_al_c : natural := 3; -- mode bit low
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constant pmp_cfg_ah_c : natural := 4; -- mode bit high
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constant pmp_cfg_l_c : natural := 7; -- locked entry
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-- data interface registers --
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-- data interface registers --
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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signal mar, mdo, mdi : std_ulogic_vector(data_width_c-1 downto 0);
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-- data access --
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-- data access --
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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signal d_bus_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- write data
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err_bus : std_ulogic; -- bus access error
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err_bus : std_ulogic; -- bus access error
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(BUS_TIMEOUT)-1 downto 0);
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end record;
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end record;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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signal i_arbiter, d_arbiter : bus_arbiter_t;
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-- physical memory protection --
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type pmp_addr34_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c+1 downto 0);
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type pmp_addr_t is array (0 to PMP_NUM_REGIONS-1) of std_ulogic_vector(data_width_c-1 downto 0);
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type pmp_t is record
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addr_mask : pmp_addr34_t; -- 34-bit
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i_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for instruction interface
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d_match : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region match for data interface
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if_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for fetch operation
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ld_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for load operation
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st_fault : std_ulogic_vector(PMP_NUM_REGIONS-1 downto 0); -- region access fault for store operation
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end record;
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signal pmp : pmp_t;
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-- pmp faults anybody? --
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signal if_pmp_fault : std_ulogic; -- pmp instruction access fault
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signal ld_pmp_fault : std_ulogic; -- pmp load access fault
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signal st_pmp_fault : std_ulogic; -- pmp store access fault
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begin
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begin
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-- Data Interface: Access Address ---------------------------------------------------------
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-- Data Interface: Access Address ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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mem_adr_reg: process(rstn_i, clk_i)
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mem_adr_reg: process(rstn_i, clk_i)
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-- instruction bus (read-only) --
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-- instruction bus (read-only) --
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i_bus_addr_o <= fetch_pc_i;
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i_bus_addr_o <= fetch_pc_i;
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i_bus_wdata_o <= (others => '0');
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i_bus_wdata_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_we_o <= '0';
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i_bus_we_o <= '0';
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned); -- no actual read when misaligned
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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instr_o <= i_bus_rdata_i;
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instr_o <= i_bus_rdata_i;
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-- Data Access Arbiter --------------------------------------------------------------------
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-- Data Access Arbiter --------------------------------------------------------------------
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ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
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ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
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be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
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be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
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ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
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ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
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be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
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be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
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-- data bus --
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-- data bus (read/write)--
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d_bus_addr_o <= mar;
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d_bus_addr_o <= mar;
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d_bus_wdata_o <= d_bus_wdata;
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d_bus_wdata_o <= d_bus_wdata;
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d_bus_ben_o <= d_bus_ben;
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d_bus_ben_o <= d_bus_ben;
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d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned); -- no actual write when misaligned
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d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
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d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned); -- no actual read when misaligned
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d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
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d_bus_rdata <= d_bus_rdata_i;
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d_bus_rdata <= d_bus_rdata_i;
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-- Physical Memory Protection (PMP) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- compute address masks --
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pmp_masks: process(pmp_addr_i, pmp, pmp_ctrl_i)
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begin
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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pmp.addr_mask(r) <= (others => '0'); -- default
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for i in PMP_GRANULARITY+2 to 33 loop
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if (i = PMP_GRANULARITY+2) then
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if (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) = pmp_napot_mode_c) then
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pmp.addr_mask(r)(i) <= '0';
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else -- OFF or unsupported mode
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pmp.addr_mask(r)(i) <= '1'; -- required for SW to check min granularity when entry is disabled
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end if;
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else
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if (pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) = pmp_napot_mode_c) then
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-- current bit = not AND(all previous bits)
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pmp.addr_mask(r)(i) <= not and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY+2));
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else -- OFF or unsupported mode
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pmp.addr_mask(r)(i) <= '1'; -- required for SW to check min granularity when entry is disabled
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end if;
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end if;
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end loop; -- i
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end loop; -- r
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end process pmp_masks;
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-- masked pmpaddr output for CSR read-back --
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pmp_masked_output: process(pmp_addr_i, pmp)
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begin
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pmp_maddr_o <= (others => (others => '0'));
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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pmp_maddr_o(r) <= pmp_addr_i(r) and pmp.addr_mask(r);
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end loop; -- r
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end process pmp_masked_output;
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-- check for access address match --
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pmp_addr_check: process (pmp, fetch_pc_i, mar, pmp_addr_i)
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variable i_cmp_v : std_ulogic_vector(31 downto 0);
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variable d_cmp_v : std_ulogic_vector(31 downto 0);
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variable b_cmp_v : std_ulogic_vector(31 downto 0);
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begin
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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b_cmp_v := pmp_addr_i(r)(33 downto 2) and pmp.addr_mask(r)(33 downto 2);
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-- instruction interface --
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i_cmp_v := fetch_pc_i and pmp.addr_mask(r)(33 downto 2);
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if (i_cmp_v(31 downto PMP_GRANULARITY+2) = b_cmp_v(31 downto PMP_GRANULARITY+2)) then
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pmp.i_match(r) <= '1';
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else
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pmp.i_match(r) <= '0';
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end if;
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-- data interface --
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d_cmp_v := mar and pmp.addr_mask(r)(33 downto 2);
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if (d_cmp_v(31 downto PMP_GRANULARITY+2) = b_cmp_v(31 downto PMP_GRANULARITY+2)) then
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pmp.d_match(r) <= '1';
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else
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pmp.d_match(r) <= '0';
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end if;
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end loop; -- r
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end process pmp_addr_check;
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-- check access type and regions's permissions --
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pmp_check_permission: process(pmp, pmp_ctrl_i, priv_mode_i)
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begin
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for r in 0 to PMP_NUM_REGIONS-1 loop -- iterate over all regions
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if ((priv_mode_i = u_priv_mode_c) or (pmp_ctrl_i(r)(pmp_cfg_l_c) = '1')) and -- user privilege level or locked pmp entry - enforce permissions also for machine mode
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(pmp_ctrl_i(r)(pmp_cfg_ah_c downto pmp_cfg_al_c) /= pmp_off_mode_c) then -- active entry
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pmp.if_fault(r) <= pmp.i_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_x_c)); -- fetch access match no execute permission
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pmp.ld_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_r_c)); -- load access match no read permission
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pmp.st_fault(r) <= pmp.d_match(r) and (not pmp_ctrl_i(r)(pmp_cfg_w_c)); -- store access match no write permission
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else
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pmp.if_fault(r) <= '0';
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pmp.ld_fault(r) <= '0';
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pmp.st_fault(r) <= '0';
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end if;
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end loop; -- r
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end process pmp_check_permission;
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-- final PMP access fault signals --
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if_pmp_fault <= or_all_f(pmp.if_fault) when (PMP_USE = true) else '0';
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ld_pmp_fault <= or_all_f(pmp.ld_fault) when (PMP_USE = true) else '0';
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st_pmp_fault <= or_all_f(pmp.st_fault) when (PMP_USE = true) else '0';
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end neorv32_cpu_bus_rtl;
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end neorv32_cpu_bus_rtl;
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