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https://opencores.org/ocsvn/neorv32/neorv32/trunk
[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_bus.vhd] - Diff between revs 30 and 31
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Rev 30 |
Rev 31 |
Line 338... |
Line 338... |
-- output instruction fetch error to controller --
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-- output instruction fetch error to controller --
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ma_instr_o <= i_arbiter.err_align;
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ma_instr_o <= i_arbiter.err_align;
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be_instr_o <= i_arbiter.err_bus;
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be_instr_o <= i_arbiter.err_bus;
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-- instruction bus (read-only) --
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-- instruction bus (read-only) --
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i_bus_addr_o <= fetch_pc_i;
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i_bus_addr_o <= fetch_pc_i(data_width_c-1 downto 2) & "00"; -- instruction access is always 4-byte aligned (even for compressed instructions)
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i_bus_wdata_o <= (others => '0');
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i_bus_wdata_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_ben_o <= (others => '0');
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i_bus_we_o <= '0';
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i_bus_we_o <= '0';
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
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