OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_cpu_bus.vhd] - Diff between revs 36 and 38

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 36 Rev 38
Line 50... Line 50...
    PMP_GRANULARITY       : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
    PMP_GRANULARITY       : natural := 16 -- granularity (1=8B, 2=16B, 3=32B, ...)
  );
  );
  port (
  port (
    -- global control --
    -- global control --
    clk_i          : in  std_ulogic; -- global clock, rising edge
    clk_i          : in  std_ulogic; -- global clock, rising edge
 
    rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
    ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
    ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
    -- cpu instruction fetch interface --
    -- cpu instruction fetch interface --
    fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
    fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
    instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
    instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
    i_wait_o       : out std_ulogic; -- wait for fetch to complete
    i_wait_o       : out std_ulogic; -- wait for fetch to complete
Line 287... Line 288...
  end process misaligned_i_check;
  end process misaligned_i_check;
 
 
 
 
  -- Instruction Fetch Arbiter --------------------------------------------------------------
  -- Instruction Fetch Arbiter --------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  ifetch_arbiter: process(clk_i)
  ifetch_arbiter: process(rstn_i, clk_i)
  begin
  begin
    if rising_edge(clk_i) then
    if (rstn_i = '0') then
 
      i_arbiter.rd_req    <= '0';
 
      i_arbiter.err_align <= '0';
 
      i_arbiter.err_bus   <= '0';
 
      i_arbiter.timeout   <= (others => '0');
 
    elsif rising_edge(clk_i) then
      -- instruction fetch request --
      -- instruction fetch request --
      if (i_arbiter.rd_req = '0') then -- idle
      if (i_arbiter.rd_req = '0') then -- idle
        i_arbiter.rd_req    <= ctrl_i(ctrl_bus_if_c);
        i_arbiter.rd_req    <= ctrl_i(ctrl_bus_if_c);
        i_arbiter.err_align <= i_misaligned;
        i_arbiter.err_align <= i_misaligned;
        i_arbiter.err_bus   <= '0';
        i_arbiter.err_bus   <= '0';
Line 331... Line 337...
  instr_o       <= i_bus_rdata_i;
  instr_o       <= i_bus_rdata_i;
 
 
 
 
  -- Data Access Arbiter --------------------------------------------------------------------
  -- Data Access Arbiter --------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  data_access_arbiter: process(clk_i)
  data_access_arbiter: process(rstn_i, clk_i)
  begin
  begin
    if rising_edge(clk_i) then
    if (rstn_i = '0') then
 
      d_arbiter.wr_req    <= '0';
 
      d_arbiter.rd_req    <= '0';
 
      d_arbiter.err_align <= '0';
 
      d_arbiter.err_bus   <= '0';
 
      d_arbiter.timeout   <= (others => '0');
 
    elsif rising_edge(clk_i) then
      -- data access request --
      -- data access request --
      if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
      if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
        d_arbiter.wr_req    <= ctrl_i(ctrl_bus_wr_c);
        d_arbiter.wr_req    <= ctrl_i(ctrl_bus_wr_c);
        d_arbiter.rd_req    <= ctrl_i(ctrl_bus_rd_c);
        d_arbiter.rd_req    <= ctrl_i(ctrl_bus_rd_c);
        d_arbiter.err_align <= d_misaligned;
        d_arbiter.err_align <= d_misaligned;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.