| Line 84... |
Line 84... |
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_re_o : out std_ulogic; -- read enable
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_err_i : in std_ulogic; -- bus transfer error
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
i_bus_fence_o : out std_ulogic; -- fence operation
|
|
i_bus_lock_o : out std_ulogic; -- locked/exclusive access
|
-- data bus --
|
-- data bus --
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_we_o : out std_ulogic; -- write enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_re_o : out std_ulogic; -- read enable
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_err_i : in std_ulogic; -- bus transfer error
|
d_bus_fence_o : out std_ulogic -- fence operation
|
d_bus_fence_o : out std_ulogic; -- fence operation
|
|
d_bus_lock_o : out std_ulogic -- locked/exclusive access
|
);
|
);
|
end neorv32_cpu_bus;
|
end neorv32_cpu_bus;
|
|
|
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
|
architecture neorv32_cpu_bus_rtl of neorv32_cpu_bus is
|
|
|
| Line 163... |
Line 165... |
-- Data Interface: Access Address ---------------------------------------------------------
|
-- Data Interface: Access Address ---------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_adr_reg: process(clk_i)
|
mem_adr_reg: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mar_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
mar <= addr_i;
|
mar <= addr_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_adr_reg;
|
end process mem_adr_reg;
|
|
|
| Line 197... |
Line 199... |
-- Data Interface: Write Data -------------------------------------------------------------
|
-- Data Interface: Write Data -------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_do_reg: process(clk_i)
|
mem_do_reg: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mdo_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mo_we_c) = '1') then
|
mdo <= wdata_i; -- memory data out register (MDO)
|
mdo <= wdata_i; -- memory data out register (MDO)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_do_reg;
|
end process mem_do_reg;
|
|
|
| Line 238... |
Line 240... |
-- Data Interface: Read Data --------------------------------------------------------------
|
-- Data Interface: Read Data --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
mem_out_buf: process(clk_i)
|
mem_out_buf: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (ctrl_i(ctrl_bus_mdi_we_c) = '1') then
|
if (ctrl_i(ctrl_bus_mi_we_c) = '1') then
|
mdi <= d_bus_rdata; -- memory data in register (MDI)
|
mdi <= d_bus_rdata; -- memory data in register (MDI)
|
end if;
|
end if;
|
end if;
|
end if;
|
end process mem_out_buf;
|
end process mem_out_buf;
|
|
|
| Line 270... |
Line 272... |
rdata_o <= mdi; -- full word
|
rdata_o <= mdi; -- full word
|
end case;
|
end case;
|
end process read_align;
|
end process read_align;
|
|
|
|
|
-- Instruction Interface: Check for Misaligned Access -------------------------------------
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
misaligned_i_check: process(ctrl_i, fetch_pc_i)
|
data_access_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
-- check instruction access --
|
if (rstn_i = '0') then
|
i_misaligned <= '0'; -- default
|
d_arbiter.wr_req <= '0';
|
if (CPU_EXTENSION_RISCV_C = true) then -- 16-bit and 32-bit instruction accesses
|
d_arbiter.rd_req <= '0';
|
i_misaligned <= '0'; -- no alignment exceptions possible
|
d_arbiter.err_align <= '0';
|
else -- 32-bit instruction accesses only
|
d_arbiter.err_bus <= '0';
|
if (fetch_pc_i(1) = '1') then -- PC(0) is always zero
|
d_arbiter.timeout <= (others => '0');
|
i_misaligned <= '1';
|
elsif rising_edge(clk_i) then
|
|
-- data access request --
|
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
|
d_arbiter.err_align <= d_misaligned;
|
|
d_arbiter.err_bus <= '0';
|
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
|
|
else -- in progress
|
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
|
d_arbiter.wr_req <= '0';
|
|
d_arbiter.rd_req <= '0';
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process misaligned_i_check;
|
end process data_access_arbiter;
|
|
|
|
-- cancel bus access --
|
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
|
|
|
-- wait for bus transaction to finish --
|
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
|
-- output data access error to controller --
|
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
|
|
|
-- data bus (read/write)--
|
|
d_bus_addr_o <= mar;
|
|
d_bus_wdata_o <= d_bus_wdata;
|
|
d_bus_ben_o <= d_bus_ben;
|
|
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
|
|
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
|
d_bus_rdata <= d_bus_rdata_i;
|
|
d_bus_lock_o <= ctrl_i(ctrl_bus_lock_c);
|
|
|
|
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- Instruction Fetch Arbiter --------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ifetch_arbiter: process(rstn_i, clk_i)
|
ifetch_arbiter: process(rstn_i, clk_i)
|
| Line 333... |
Line 372... |
i_bus_ben_o <= (others => '0');
|
i_bus_ben_o <= (others => '0');
|
i_bus_we_o <= '0';
|
i_bus_we_o <= '0';
|
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
|
i_bus_re_o <= ctrl_i(ctrl_bus_if_c) and (not i_misaligned) and (not if_pmp_fault); -- no actual read when misaligned or PMP fault
|
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
|
i_bus_fence_o <= ctrl_i(ctrl_bus_fencei_c);
|
instr_o <= i_bus_rdata_i;
|
instr_o <= i_bus_rdata_i;
|
|
i_bus_lock_o <= '0'; -- instruction fetch cannot be atomic
|
|
|
|
|
-- Data Access Arbiter --------------------------------------------------------------------
|
-- check instruction access --
|
-- -------------------------------------------------------------------------------------------
|
i_misaligned <= '0' when (CPU_EXTENSION_RISCV_C = true) else -- no alignment exceptions possible when using C-extension
|
data_access_arbiter: process(rstn_i, clk_i)
|
'1' when (fetch_pc_i(1) = '1') else '0'; -- 32-bit accesses only
|
begin
|
|
if (rstn_i = '0') then
|
|
d_arbiter.wr_req <= '0';
|
|
d_arbiter.rd_req <= '0';
|
|
d_arbiter.err_align <= '0';
|
|
d_arbiter.err_bus <= '0';
|
|
d_arbiter.timeout <= (others => '0');
|
|
elsif rising_edge(clk_i) then
|
|
-- data access request --
|
|
if (d_arbiter.wr_req = '0') and (d_arbiter.rd_req = '0') then -- idle
|
|
d_arbiter.wr_req <= ctrl_i(ctrl_bus_wr_c);
|
|
d_arbiter.rd_req <= ctrl_i(ctrl_bus_rd_c);
|
|
d_arbiter.err_align <= d_misaligned;
|
|
d_arbiter.err_bus <= '0';
|
|
d_arbiter.timeout <= std_ulogic_vector(to_unsigned(bus_timeout_c, index_size_f(bus_timeout_c)));
|
|
else -- in progress
|
|
d_arbiter.timeout <= std_ulogic_vector(unsigned(d_arbiter.timeout) - 1);
|
|
d_arbiter.err_align <= (d_arbiter.err_align or d_misaligned) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
|
d_arbiter.err_bus <= (d_arbiter.err_bus or (not or_all_f(d_arbiter.timeout)) or d_bus_err_i) and (not ctrl_i(ctrl_bus_derr_ack_c));
|
|
if (d_bus_ack_i = '1') or (ctrl_i(ctrl_bus_derr_ack_c) = '1') then -- wait for normal termination / CPU abort
|
|
d_arbiter.wr_req <= '0';
|
|
d_arbiter.rd_req <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process data_access_arbiter;
|
|
|
|
-- cancel bus access --
|
|
d_bus_cancel_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and ctrl_i(ctrl_bus_derr_ack_c);
|
|
|
|
-- wait for bus transaction to finish --
|
|
d_wait_o <= (d_arbiter.wr_req or d_arbiter.rd_req) and (not d_bus_ack_i);
|
|
|
|
-- output data access error to controller --
|
|
ma_load_o <= d_arbiter.rd_req and d_arbiter.err_align;
|
|
be_load_o <= d_arbiter.rd_req and d_arbiter.err_bus;
|
|
ma_store_o <= d_arbiter.wr_req and d_arbiter.err_align;
|
|
be_store_o <= d_arbiter.wr_req and d_arbiter.err_bus;
|
|
|
|
-- data bus (read/write)--
|
|
d_bus_addr_o <= mar;
|
|
d_bus_wdata_o <= d_bus_wdata;
|
|
d_bus_ben_o <= d_bus_ben;
|
|
d_bus_we_o <= ctrl_i(ctrl_bus_wr_c) and (not d_misaligned) and (not st_pmp_fault); -- no actual write when misaligned or PMP fault
|
|
d_bus_re_o <= ctrl_i(ctrl_bus_rd_c) and (not d_misaligned) and (not ld_pmp_fault); -- no actual read when misaligned or PMP fault
|
|
d_bus_fence_o <= ctrl_i(ctrl_bus_fence_c);
|
|
d_bus_rdata <= d_bus_rdata_i;
|
|
|
|
|
|
-- Physical Memory Protection (PMP) -------------------------------------------------------
|
-- Physical Memory Protection (PMP) -------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- compute address masks --
|
-- compute address masks --
|
| Line 399... |
Line 392... |
pmp.addr_mask(r) <= (others => '0'); -- default
|
pmp.addr_mask(r) <= (others => '0'); -- default
|
for i in PMP_GRANULARITY+1 to 33 loop
|
for i in PMP_GRANULARITY+1 to 33 loop
|
if (i = PMP_GRANULARITY+1) then
|
if (i = PMP_GRANULARITY+1) then
|
pmp.addr_mask(r)(i) <= '0';
|
pmp.addr_mask(r)(i) <= '0';
|
else -- current bit = not AND(all previous bits)
|
else -- current bit = not AND(all previous bits)
|
pmp.addr_mask(r)(i) <= not (and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY)));
|
pmp.addr_mask(r)(i) <= not and_all_f(pmp_addr_i(r)(i-1 downto PMP_GRANULARITY));
|
end if;
|
end if;
|
end loop; -- i
|
end loop; -- i
|
end loop; -- r
|
end loop; -- r
|
end if;
|
end if;
|
end process pmp_masks;
|
end process pmp_masks;
|
